hi3670.dtsi (715a1284d89a740b197b3bad5eb20d36a397382f) hi3670.dtsi (305656e0989d45e8dc7273e62130f3dc79d3e2de)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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189 };
190
191 media2_crg: media2_crgctrl@e8900000 {
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
193 reg = <0x0 0xe8900000 0x0 0x1000>;
194 #clock-cells = <1>;
195 };
196
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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189 };
190
191 media2_crg: media2_crgctrl@e8900000 {
192 compatible = "hisilicon,hi3670-media2-crg","syscon";
193 reg = <0x0 0xe8900000 0x0 0x1000>;
194 #clock-cells = <1>;
195 };
196
197 iomcu_rst: reset {
198 compatible = "hisilicon,hi3660-reset";
199 hisi,rst-syscon = <&iomcu>;
200 #reset-cells = <2>;
201 };
202
197 uart0: serial@fdf02000 {
198 compatible = "arm,pl011", "arm,primecell";
199 reg = <0x0 0xfdf02000 0x0 0x1000>;
200 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
202 <&crg_ctrl HI3670_PCLK>;
203 clock-names = "uartclk", "apb_pclk";
204 pinctrl-names = "default";

--- 508 unchanged lines hidden --- 		203 uart0: serial@fdf02000 {
204 compatible = "arm,pl011", "arm,primecell";
205 reg = <0x0 0xfdf02000 0x0 0x1000>;
206 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&crg_ctrl HI3670_CLK_GATE_UART0>,
208 <&crg_ctrl HI3670_PCLK>;
209 clock-names = "uartclk", "apb_pclk";
210 pinctrl-names = "default";

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