hi3670.dtsi (1136fa0c07de570dc17858745af8be169d1440ba) hi3670.dtsi (65b96377bf9130617ced41f317f3ec387d3e0dc3)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, HiSilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

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666 /* 1: UFS SYS CTRL */
667 reg = <0x0 0xff3c0000 0x0 0x1000>,
668 <0x0 0xff3e0000 0x0 0x1000>;
669 interrupt-parent = <&gic>;
670 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
672 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
673 clock-names = "ref_clk", "phy_clk";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3670 SoC
4 *
5 * Copyright (C) 2016, HiSilicon Ltd.
6 * Copyright (C) 2018, Linaro Ltd.
7 */
8

--- 657 unchanged lines hidden (view full) ---

666 /* 1: UFS SYS CTRL */
667 reg = <0x0 0xff3c0000 0x0 0x1000>,
668 <0x0 0xff3e0000 0x0 0x1000>;
669 interrupt-parent = <&gic>;
670 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
672 <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
673 clock-names = "ref_clk", "phy_clk";
674 freq-table-hz = <0 0
675 0 0>;
674 freq-table-hz = <0 0>,
675 <0 0>;
676 /* offset: 0x84; bit: 12 */
677 resets = <&crg_rst 0x84 12>;
678 reset-names = "rst";
679 };
680
681 /* SD */
682 dwmmc1: dwmmc1@ff37f000 {
683 compatible = "hisilicon,hi3670-dw-mshc",

--- 106 unchanged lines hidden --- 		676 /* offset: 0x84; bit: 12 */
677 resets = <&crg_rst 0x84 12>;
678 reset-names = "rst";
679 };
680
681 /* SD */
682 dwmmc1: dwmmc1@ff37f000 {
683 compatible = "hisilicon,hi3670-dw-mshc",

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