hi3660.dtsi (1136fa0c07de570dc17858745af8be169d1440ba) hi3660.dtsi (65b96377bf9130617ced41f317f3ec387d3e0dc3)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, HiSilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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1040 /* 1: UFS SYS CTRL */
1041 reg = <0x0 0xff3b0000 0x0 0x1000>,
1042 <0x0 0xff3b1000 0x0 0x1000>;
1043 interrupt-parent = <&gic>;
1044 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1046 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1047 clock-names = "ref_clk", "phy_clk";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, HiSilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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1040 /* 1: UFS SYS CTRL */
1041 reg = <0x0 0xff3b0000 0x0 0x1000>,
1042 <0x0 0xff3b1000 0x0 0x1000>;
1043 interrupt-parent = <&gic>;
1044 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1046 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1047 clock-names = "ref_clk", "phy_clk";
1048 freq-table-hz = <0 0
1049 0 0>;
1048 freq-table-hz = <0 0>,
1049 <0 0>;
1050 /* offset: 0x84; bit: 12 */
1051 resets = <&crg_rst 0x84 12>;
1052 reset-names = "rst";
1053 };
1054
1055 /* SD */
1056 dwmmc1: dwmmc1@ff37f000 {
1057 compatible = "hisilicon,hi3660-dw-mshc";

--- 138 unchanged lines hidden --- 		1050 /* offset: 0x84; bit: 12 */
1051 resets = <&crg_rst 0x84 12>;
1052 reset-names = "rst";
1053 };
1054
1055 /* SD */
1056 dwmmc1: dwmmc1@ff37f000 {
1057 compatible = "hisilicon,hi3660-dw-mshc";

--- 138 unchanged lines hidden ---