hi3660.dtsi (05909cd9a0c8811731b38697af13075e8954314f) hi3660.dtsi (8c563f55ee1d0241b834dd4b43be11cf7a47732b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 1031 unchanged lines hidden (view full) ---

1040 /* 1: UFS SYS CTRL */
1041 reg = <0x0 0xff3b0000 0x0 0x1000>,
1042 <0x0 0xff3b1000 0x0 0x1000>;
1043 interrupt-parent = <&gic>;
1044 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1046 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1047 clock-names = "ref_clk", "phy_clk";
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Hisilicon Hi3660 SoC
4 *
5 * Copyright (C) 2016, Hisilicon Ltd.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 1031 unchanged lines hidden (view full) ---

1040 /* 1: UFS SYS CTRL */
1041 reg = <0x0 0xff3b0000 0x0 0x1000>,
1042 <0x0 0xff3b1000 0x0 0x1000>;
1043 interrupt-parent = <&gic>;
1044 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1046 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1047 clock-names = "ref_clk", "phy_clk";
1048 freq-table-hz = <0 0>, <0 0>;
1048 freq-table-hz = <0 0
1049 0 0>;
1049 /* offset: 0x84; bit: 12 */
1050 resets = <&crg_rst 0x84 12>;
1051 reset-names = "rst";
1052 };
1053
1054 /* SD */
1055 dwmmc1: dwmmc1@ff37f000 {
1056 compatible = "hisilicon,hi3660-dw-mshc";

--- 27 unchanged lines hidden (view full) ---

1084 card-detect-delay = <200>;
1085 status = "disabled";
1086 };
1087
1088 watchdog0: watchdog@e8a06000 {
1089 compatible = "arm,sp805-wdt", "arm,primecell";
1090 reg = <0x0 0xe8a06000 0x0 0x1000>;
1091 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1050 /* offset: 0x84; bit: 12 */
1051 resets = <&crg_rst 0x84 12>;
1052 reset-names = "rst";
1053 };
1054
1055 /* SD */
1056 dwmmc1: dwmmc1@ff37f000 {
1057 compatible = "hisilicon,hi3660-dw-mshc";

--- 27 unchanged lines hidden (view full) ---

1085 card-detect-delay = <200>;
1086 status = "disabled";
1087 };
1088
1089 watchdog0: watchdog@e8a06000 {
1090 compatible = "arm,sp805-wdt", "arm,primecell";
1091 reg = <0x0 0xe8a06000 0x0 0x1000>;
1092 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&crg_ctrl HI3660_OSC32K>;
1093 clock-names = "apb_pclk";
1093 clocks = <&crg_ctrl HI3660_OSC32K>,
1094 <&crg_ctrl HI3660_OSC32K>;
1095 clock-names = "wdog_clk", "apb_pclk";
1094 };
1095
1096 watchdog1: watchdog@e8a07000 {
1097 compatible = "arm,sp805-wdt", "arm,primecell";
1098 reg = <0x0 0xe8a07000 0x0 0x1000>;
1099 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1096 };
1097
1098 watchdog1: watchdog@e8a07000 {
1099 compatible = "arm,sp805-wdt", "arm,primecell";
1100 reg = <0x0 0xe8a07000 0x0 0x1000>;
1101 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1100 clocks = <&crg_ctrl HI3660_OSC32K>;
1101 clock-names = "apb_pclk";
1102 clocks = <&crg_ctrl HI3660_OSC32K>,
1103 <&crg_ctrl HI3660_OSC32K>;
1104 clock-names = "wdog_clk", "apb_pclk";
1102 };
1103
1104 tsensor: tsensor@fff30000 {
1105 compatible = "hisilicon,hi3660-tsensor";
1106 reg = <0x0 0xfff30000 0x0 0x1000>;
1107 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1108 #thermal-sensor-cells = <1>;
1109 };

--- 83 unchanged lines hidden --- 		1105 };
1106
1107 tsensor: tsensor@fff30000 {
1108 compatible = "hisilicon,hi3660-tsensor";
1109 reg = <0x0 0xfff30000 0x0 0x1000>;
1110 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1111 #thermal-sensor-cells = <1>;
1112 };

--- 83 unchanged lines hidden ---