exynos7885.dtsi (f84d83d8165570380f55f4ce578bfb131a9266c5) exynos7885.dtsi (ced37411d7f597129fecc0c3ca2324f44e33f4c8)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos7885 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2021 Dávid Virág
7 */
8

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235 compatible = "samsung,exynos7885-cmu-top";
236 reg = <0x12060000 0x8000>;
237 #clock-cells = <1>;
238
239 clocks = <&oscclk>;
240 clock-names = "oscclk";
241 };
242
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos7885 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2021 Dávid Virág
7 */
8

--- 226 unchanged lines hidden (view full) ---

235 compatible = "samsung,exynos7885-cmu-top";
236 reg = <0x12060000 0x8000>;
237 #clock-cells = <1>;
238
239 clocks = <&oscclk>;
240 clock-names = "oscclk";
241 };
242
243 cmu_fsys: clock-controller@13400000 {
244 compatible = "samsung,exynos7885-cmu-fsys";
245 reg = <0x13400000 0x8000>;
246 #clock-cells = <1>;
247
248 clocks = <&oscclk>,
249 <&cmu_top CLK_DOUT_FSYS_BUS>,
250 <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
251 <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
252 <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
253 <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
254 clock-names = "oscclk",
255 "dout_fsys_bus",
256 "dout_fsys_mmc_card",
257 "dout_fsys_mmc_embd",
258 "dout_fsys_mmc_sdio",
259 "dout_fsys_usb30drd";
260 };
261
243 pinctrl_alive: pinctrl@11cb0000 {
244 compatible = "samsung,exynos7885-pinctrl";
245 reg = <0x11cb0000 0x1000>;
246
247 wakeup-interrupt-controller {
248 compatible = "samsung,exynos7-wakeup-eint";
249 interrupt-parent = <&gic>;
250 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;

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269 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
270 };
271
272 pmu_system_controller: system-controller@11c80000 {
273 compatible = "samsung,exynos7-pmu", "syscon";
274 reg = <0x11c80000 0x10000>;
275 };
276
262 pinctrl_alive: pinctrl@11cb0000 {
263 compatible = "samsung,exynos7885-pinctrl";
264 reg = <0x11cb0000 0x1000>;
265
266 wakeup-interrupt-controller {
267 compatible = "samsung,exynos7-wakeup-eint";
268 interrupt-parent = <&gic>;
269 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;

--- 18 unchanged lines hidden (view full) ---

288 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
289 };
290
291 pmu_system_controller: system-controller@11c80000 {
292 compatible = "samsung,exynos7-pmu", "syscon";
293 reg = <0x11c80000 0x10000>;
294 };
295
296 mmc_0: mmc@13500000 {
297 compatible = "samsung,exynos7-dw-mshc-smu";
298 reg = <0x13500000 0x2000>;
299 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
303 <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
304 clock-names = "biu", "ciu";
305 fifo-depth = <0x40>;
306 status = "disabled";
307 };
308
277 serial_0: serial@13800000 {
278 compatible = "samsung,exynos5433-uart";
279 reg = <0x13800000 0x100>;
280 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart0_bus>;
309 serial_0: serial@13800000 {
310 compatible = "samsung,exynos5433-uart";
311 reg = <0x13800000 0x100>;
312 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&uart0_bus>;
283 clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
284 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
315 clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
316 <&cmu_peri CLK_GOUT_UART0_PCLK>;
285 clock-names = "uart", "clk_uart_baud0";
286 samsung,uart-fifosize = <64>;
287 status = "disabled";
288 };
289
290 serial_1: serial@13810000 {
291 compatible = "samsung,exynos5433-uart";
292 reg = <0x13810000 0x100>;
293 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&uart1_bus>;
317 clock-names = "uart", "clk_uart_baud0";
318 samsung,uart-fifosize = <64>;
319 status = "disabled";
320 };
321
322 serial_1: serial@13810000 {
323 compatible = "samsung,exynos5433-uart";
324 reg = <0x13810000 0x100>;
325 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&uart1_bus>;
296 clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
297 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
328 clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
329 <&cmu_peri CLK_GOUT_UART1_PCLK>;
298 clock-names = "uart", "clk_uart_baud0";
299 samsung,uart-fifosize = <256>;
300 status = "disabled";
301 };
302
303 serial_2: serial@13820000 {
304 compatible = "samsung,exynos5433-uart";
305 reg = <0x13820000 0x100>;
306 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart2_bus>;
330 clock-names = "uart", "clk_uart_baud0";
331 samsung,uart-fifosize = <256>;
332 status = "disabled";
333 };
334
335 serial_2: serial@13820000 {
336 compatible = "samsung,exynos5433-uart";
337 reg = <0x13820000 0x100>;
338 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart2_bus>;
309 clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
310 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
341 clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
342 <&cmu_peri CLK_GOUT_UART2_PCLK>;
311 clock-names = "uart", "clk_uart_baud0";
312 samsung,uart-fifosize = <256>;
313 status = "disabled";
314 };
315
316 i2c_0: i2c@13830000 {
317 compatible = "samsung,s3c2440-i2c";
318 reg = <0x13830000 0x100>;

--- 105 unchanged lines hidden --- 		343 clock-names = "uart", "clk_uart_baud0";
344 samsung,uart-fifosize = <256>;
345 status = "disabled";
346 };
347
348 i2c_0: i2c@13830000 {
349 compatible = "samsung,s3c2440-i2c";
350 reg = <0x13830000 0x100>;

--- 105 unchanged lines hidden ---