exynos7885.dtsi (03ab8e6297acd1bc0eedaa050e2a1635c576fd11) exynos7885.dtsi (f84d83d8165570380f55f4ce578bfb131a9266c5)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos7885 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2021 Dávid Virág
7 */
8

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275 };
276
277 serial_0: serial@13800000 {
278 compatible = "samsung,exynos5433-uart";
279 reg = <0x13800000 0x100>;
280 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart0_bus>;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung Exynos7885 SoC device tree source
4 *
5 * Copyright (c) 2021 Samsung Electronics Co., Ltd.
6 * Copyright (c) 2021 Dávid Virág
7 */
8

--- 266 unchanged lines hidden (view full) ---

275 };
276
277 serial_0: serial@13800000 {
278 compatible = "samsung,exynos5433-uart";
279 reg = <0x13800000 0x100>;
280 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart0_bus>;
283 clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
284 <&cmu_peri CLK_GOUT_UART0_PCLK>;
283 clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
284 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
285 clock-names = "uart", "clk_uart_baud0";
286 samsung,uart-fifosize = <64>;
287 status = "disabled";
288 };
289
290 serial_1: serial@13810000 {
291 compatible = "samsung,exynos5433-uart";
292 reg = <0x13810000 0x100>;
293 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&uart1_bus>;
285 clock-names = "uart", "clk_uart_baud0";
286 samsung,uart-fifosize = <64>;
287 status = "disabled";
288 };
289
290 serial_1: serial@13810000 {
291 compatible = "samsung,exynos5433-uart";
292 reg = <0x13810000 0x100>;
293 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&uart1_bus>;
296 clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
297 <&cmu_peri CLK_GOUT_UART1_PCLK>;
296 clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
297 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
298 clock-names = "uart", "clk_uart_baud0";
299 samsung,uart-fifosize = <256>;
300 status = "disabled";
301 };
302
303 serial_2: serial@13820000 {
304 compatible = "samsung,exynos5433-uart";
305 reg = <0x13820000 0x100>;
306 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart2_bus>;
298 clock-names = "uart", "clk_uart_baud0";
299 samsung,uart-fifosize = <256>;
300 status = "disabled";
301 };
302
303 serial_2: serial@13820000 {
304 compatible = "samsung,exynos5433-uart";
305 reg = <0x13820000 0x100>;
306 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&uart2_bus>;
309 clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
310 <&cmu_peri CLK_GOUT_UART2_PCLK>;
309 clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
310 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
311 clock-names = "uart", "clk_uart_baud0";
312 samsung,uart-fifosize = <256>;
313 status = "disabled";
314 };
315
316 i2c_0: i2c@13830000 {
317 compatible = "samsung,s3c2440-i2c";
318 reg = <0x13830000 0x100>;

--- 105 unchanged lines hidden --- 		311 clock-names = "uart", "clk_uart_baud0";
312 samsung,uart-fifosize = <256>;
313 status = "disabled";
314 };
315
316 i2c_0: i2c@13830000 {
317 compatible = "samsung,s3c2440-i2c";
318 reg = <0x13830000 0x100>;

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