stingray.dtsi (c6bb11147eb09bd39f316c6062455b88c905ab6e) stingray.dtsi (133de204e4741af76b101e101c58e0cd1676a887)
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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141 timer {
142 compatible = "arm,armv8-timer";
143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
147 };
148
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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141 timer {
142 compatible = "arm,armv8-timer";
143 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
147 };
148
149 mhb: syscon@60401000 {
150 compatible = "brcm,sr-mhb", "syscon";
151 reg = <0 0x60401000 0 0x38c>;
152 };
153
149 scr {
150 compatible = "simple-bus";
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges = <0x0 0x0 0x61000000 0x05000000>;
154
155 ccn: ccn@0 {
156 compatible = "arm,ccn-502";

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253 crmu: crmu {
254 compatible = "simple-bus";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges = <0x0 0x0 0x66400000 0x100000>;
258
259 #include "stingray-clock.dtsi"
260
154 scr {
155 compatible = "simple-bus";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 ranges = <0x0 0x0 0x61000000 0x05000000>;
159
160 ccn: ccn@0 {
161 compatible = "arm,ccn-502";

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258 crmu: crmu {
259 compatible = "simple-bus";
260 #address-cells = <1>;
261 #size-cells = <1>;
262 ranges = <0x0 0x0 0x66400000 0x100000>;
263
264 #include "stingray-clock.dtsi"
265
266 otp: otp@1c400 {
267 compatible = "brcm,ocotp-v2";
268 reg = <0x0001c400 0x68>;
269 brcm,ocotp-size = <2048>;
270 status = "okay";
271 };
272
273 cdru: syscon@1d000 {
274 compatible = "brcm,sr-cdru", "syscon";
275 reg = <0x0001d000 0x400>;
276 };
277
261 gpio_crmu: gpio@24800 {
262 compatible = "brcm,iproc-gpio";
263 reg = <0x00024800 0x4c>;
264 ngpios = <6>;
265 #gpio-cells = <2>;
266 gpio-controller;
267 };
268 };
269
270 #include "stingray-fs4.dtsi"
271 #include "stingray-sata.dtsi"
278 gpio_crmu: gpio@24800 {
279 compatible = "brcm,iproc-gpio";
280 reg = <0x00024800 0x4c>;
281 ngpios = <6>;
282 #gpio-cells = <2>;
283 gpio-controller;
284 };
285 };
286
287 #include "stingray-fs4.dtsi"
288 #include "stingray-sata.dtsi"
289 #include "stingray-pcie.dtsi"
272
273 hsls {
274 compatible = "simple-bus";
275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges = <0x0 0x0 0x68900000 0x17700000>;
278
279 #include "stingray-pinctrl.dtsi"

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404 status = "disabled";
405 };
406
407 i2c0: i2c@b0000 {
408 compatible = "brcm,iproc-i2c";
409 reg = <0x000b0000 0x100>;
410 #address-cells = <1>;
411 #size-cells = <0>;
290
291 hsls {
292 compatible = "simple-bus";
293 #address-cells = <1>;
294 #size-cells = <1>;
295 ranges = <0x0 0x0 0x68900000 0x17700000>;
296
297 #include "stingray-pinctrl.dtsi"

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422 status = "disabled";
423 };
424
425 i2c0: i2c@b0000 {
426 compatible = "brcm,iproc-i2c";
427 reg = <0x000b0000 0x100>;
428 #address-cells = <1>;
429 #size-cells = <0>;
412 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
430 interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
413 clock-frequency = <100000>;
414 status = "disabled";
415 };
416
417 wdt0: watchdog@c0000 {
418 compatible = "arm,sp805", "arm,primecell";
419 reg = <0x000c0000 0x1000>;
420 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
422 clock-names = "wdogclk", "apb_pclk";
431 clock-frequency = <100000>;
432 status = "disabled";
433 };
434
435 wdt0: watchdog@c0000 {
436 compatible = "arm,sp805", "arm,primecell";
437 reg = <0x000c0000 0x1000>;
438 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
440 clock-names = "wdogclk", "apb_pclk";
441 timeout-sec = <60>;
423 };
424
425 gpio_hsls: gpio@d0000 {
426 compatible = "brcm,iproc-gpio";
427 reg = <0x000d0000 0x864>;
428 ngpios = <151>;
429 #gpio-cells = <2>;
430 gpio-controller;

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448 <&pinmux 151 91 4>;
449 };
450
451 i2c1: i2c@e0000 {
452 compatible = "brcm,iproc-i2c";
453 reg = <0x000e0000 0x100>;
454 #address-cells = <1>;
455 #size-cells = <0>;
442 };
443
444 gpio_hsls: gpio@d0000 {
445 compatible = "brcm,iproc-gpio";
446 reg = <0x000d0000 0x864>;
447 ngpios = <151>;
448 #gpio-cells = <2>;
449 gpio-controller;

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467 <&pinmux 151 91 4>;
468 };
469
470 i2c1: i2c@e0000 {
471 compatible = "brcm,iproc-i2c";
472 reg = <0x000e0000 0x100>;
473 #address-cells = <1>;
474 #size-cells = <0>;
456 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
475 interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
457 clock-frequency = <100000>;
458 status = "disabled";
459 };
460
461 uart0: uart@100000 {
462 device_type = "serial";
463 compatible = "snps,dw-apb-uart";
464 reg = <0x00100000 0x1000>;

--- 132 unchanged lines hidden --- 		476 clock-frequency = <100000>;
477 status = "disabled";
478 };
479
480 uart0: uart@100000 {
481 device_type = "serial";
482 compatible = "snps,dw-apb-uart";
483 reg = <0x00100000 0x1000>;

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