bcm4912.dtsi (7ae9fb1b7ecbb5d85d07857943f677fd1a559b18) | bcm4912.dtsi (f5d83b714e304d5f3229da434af2eeea033c4f5d) |
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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 --- 65 unchanged lines hidden (view full) --- 74 }; 75 76 clocks: clocks { 77 periph_clk: periph-clk { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <200000000>; 81 }; | 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 --- 65 unchanged lines hidden (view full) --- 74 }; 75 76 clocks: clocks { 77 periph_clk: periph-clk { 78 compatible = "fixed-clock"; 79 #clock-cells = <0>; 80 clock-frequency = <200000000>; 81 }; |
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82 uart_clk: uart-clk { 83 compatible = "fixed-factor-clock"; 84 #clock-cells = <0>; 85 clocks = <&periph_clk>; 86 clock-div = <4>; 87 clock-mult = <1>; 88 }; | 83 uart_clk: uart-clk { 84 compatible = "fixed-factor-clock"; 85 #clock-cells = <0>; 86 clocks = <&periph_clk>; 87 clock-div = <4>; 88 clock-mult = <1>; 89 }; |
90 91 hsspi_pll: hsspi-pll { 92 compatible = "fixed-clock"; 93 #clock-cells = <0>; 94 clock-frequency = <200000000>; 95 }; |
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89 }; 90 91 psci { 92 compatible = "arm,psci-0.2"; 93 method = "smc"; 94 }; 95 96 axi@81000000 { --- 15 unchanged lines hidden (view full) --- 112 }; 113 114 bus@ff800000 { 115 compatible = "simple-bus"; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0x0 0x0 0xff800000 0x800000>; 119 | 96 }; 97 98 psci { 99 compatible = "arm,psci-0.2"; 100 method = "smc"; 101 }; 102 103 axi@81000000 { --- 15 unchanged lines hidden (view full) --- 119 }; 120 121 bus@ff800000 { 122 compatible = "simple-bus"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0x0 0x0 0xff800000 0x800000>; 126 |
127 hsspi: spi@1000 { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1"; 131 reg = <0x1000 0x600>, <0x2610 0x4>; 132 reg-names = "hsspi", "spim-ctrl"; 133 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&hsspi_pll &hsspi_pll>; 135 clock-names = "hsspi", "pll"; 136 num-cs = <8>; 137 status = "disabled"; 138 }; 139 |
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120 uart0: serial@12000 { 121 compatible = "arm,pl011", "arm,primecell"; 122 reg = <0x12000 0x1000>; 123 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&uart_clk>, <&uart_clk>; 125 clock-names = "uartclk", "apb_pclk"; 126 status = "disabled"; 127 }; 128 }; 129}; | 140 uart0: serial@12000 { 141 compatible = "arm,pl011", "arm,primecell"; 142 reg = <0x12000 0x1000>; 143 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&uart_clk>, <&uart_clk>; 145 clock-names = "uartclk", "apb_pclk"; 146 status = "disabled"; 147 }; 148 }; 149}; |