| proc-v6.S (25985edcedea6396277003854657b5f3cb31a628) | proc-v6.S (29ea23ff905d07d8559bac69cca46f4bbf20038c) |
|---|---|
| 1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 110 unchanged lines hidden (view full) --- 119#ifdef CONFIG_MMU 120 armv6_set_pte_ext cpu_v6 121#endif 122 mov pc, lr 123 124/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 125.globl cpu_v6_suspend_size 126.equ cpu_v6_suspend_size, 4 * 8 | 1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 110 unchanged lines hidden (view full) --- 119#ifdef CONFIG_MMU 120 armv6_set_pte_ext cpu_v6 121#endif 122 mov pc, lr 123 124/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 125.globl cpu_v6_suspend_size 126.equ cpu_v6_suspend_size, 4 * 8 |
| 127#ifdef CONFIG_PM | 127#ifdef CONFIG_PM_SLEEP |
| 128ENTRY(cpu_v6_do_suspend) 129 stmfd sp!, {r4 - r11, lr} 130 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 131 mrc p15, 0, r5, c13, c0, 1 @ Context ID 132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 | 128ENTRY(cpu_v6_do_suspend) 129 stmfd sp!, {r4 - r11, lr} 130 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 131 mrc p15, 0, r5, c13, c0, 1 @ Context ID 132 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 133 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 134 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 |
| 135 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register | 135 mrc p15, 0, r9, c1, c0, 1 @ auxillary control register |
| 136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control 137 mrc p15, 0, r11, c1, c0, 0 @ control register 138 stmia r0, {r4 - r11} 139 ldmfd sp!, {r4- r11, pc} 140ENDPROC(cpu_v6_do_suspend) 141 142ENTRY(cpu_v6_do_resume) 143 mov ip, #0 144 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 145 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 146 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 147 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 148 ldmia r0, {r4 - r11} 149 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 150 mcr p15, 0, r5, c13, c0, 1 @ Context ID 151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 | 136 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control 137 mrc p15, 0, r11, c1, c0, 0 @ control register 138 stmia r0, {r4 - r11} 139 ldmfd sp!, {r4- r11, pc} 140ENDPROC(cpu_v6_do_suspend) 141 142ENTRY(cpu_v6_do_resume) 143 mov ip, #0 144 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 145 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 146 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 147 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 148 ldmia r0, {r4 - r11} 149 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 150 mcr p15, 0, r5, c13, c0, 1 @ Context ID 151 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 152 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 153 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 |
| 154 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register | 154 mcr p15, 0, r9, c1, c0, 1 @ auxillary control register |
| 155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control 156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 157 mcr p15, 0, ip, c7, c5, 4 @ ISB 158 mov r0, r11 @ control register 159 mov r2, r7, lsr #14 @ get TTB0 base 160 mov r2, r2, lsl #14 161 ldr r3, cpu_resume_l1_flags 162 b cpu_resume_mmu --- 174 unchanged lines hidden --- | 155 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control 156 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 157 mcr p15, 0, ip, c7, c5, 4 @ ISB 158 mov r0, r11 @ control register 159 mov r2, r7, lsr #14 @ get TTB0 base 160 mov r2, r2, lsl #14 161 ldr r3, cpu_resume_l1_flags 162 b cpu_resume_mmu --- 174 unchanged lines hidden --- |