cache-v4.S (accba5f3965d6a9d1bf7c1e1a7995d17e9d521b6) cache-v4.S (e4d2a5985af957d2c0da61fb978d0c414b92a562)
1/*
2 * linux/arch/arm/mm/cache-v4.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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24ENTRY(v4_flush_user_cache_all)
25 /* FALLTHROUGH */
26/*
27 * flush_kern_cache_all()
28 *
29 * Clean and invalidate the entire cache.
30 */
31ENTRY(v4_flush_kern_cache_all)
1/*
2 * linux/arch/arm/mm/cache-v4.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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24ENTRY(v4_flush_user_cache_all)
25 /* FALLTHROUGH */
26/*
27 * flush_kern_cache_all()
28 *
29 * Clean and invalidate the entire cache.
30 */
31ENTRY(v4_flush_kern_cache_all)
32#ifdef CPU_CP15
32#ifdef CONFIG_CPU_CP15
33 mov r0, #0
34 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
35 mov pc, lr
36#else
37 /* FALLTHROUGH */
38#endif
39
40/*
41 * flush_user_cache_range(start, end, flags)
42 *
43 * Invalidate a range of cache entries in the specified
44 * address space.
45 *
46 * - start - start address (may not be aligned)
47 * - end - end address (exclusive, may not be aligned)
48 * - flags - vma_area_struct flags describing address space
49 */
50ENTRY(v4_flush_user_cache_range)
33 mov r0, #0
34 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
35 mov pc, lr
36#else
37 /* FALLTHROUGH */
38#endif
39
40/*
41 * flush_user_cache_range(start, end, flags)
42 *
43 * Invalidate a range of cache entries in the specified
44 * address space.
45 *
46 * - start - start address (may not be aligned)
47 * - end - end address (exclusive, may not be aligned)
48 * - flags - vma_area_struct flags describing address space
49 */
50ENTRY(v4_flush_user_cache_range)
51#ifdef CPU_CP15
51#ifdef CONFIG_CPU_CP15
52 mov ip, #0
53 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
54 mov pc, lr
55#else
56 /* FALLTHROUGH */
57#endif
58
59/*

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111 * dma_flush_range(start, end)
112 *
113 * Clean and invalidate the specified virtual address range.
114 *
115 * - start - virtual start address
116 * - end - virtual end address
117 */
118ENTRY(v4_dma_flush_range)
52 mov ip, #0
53 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
54 mov pc, lr
55#else
56 /* FALLTHROUGH */
57#endif
58
59/*

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111 * dma_flush_range(start, end)
112 *
113 * Clean and invalidate the specified virtual address range.
114 *
115 * - start - virtual start address
116 * - end - virtual end address
117 */
118ENTRY(v4_dma_flush_range)
119#ifdef CPU_CP15
119#ifdef CONFIG_CPU_CP15
120 mov r0, #0
121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
122#endif
123 /* FALLTHROUGH */
124
125/*
126 * dma_clean_range(start, end)
127 *

--- 22 unchanged lines hidden --- 		120 mov r0, #0
121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
122#endif
123 /* FALLTHROUGH */
124
125/*
126 * dma_clean_range(start, end)
127 *

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