cache-v4.S (1da177e4c3f41524e886b7f1b8a0c1fc7321cac2) cache-v4.S (f12d0d7c7786af39435ef6ae9defe47fb58f6091)
1/*
2 * linux/arch/arm/mm/cache-v4.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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24ENTRY(v4_flush_user_cache_all)
25 /* FALLTHROUGH */
26/*
27 * flush_kern_cache_all()
28 *
29 * Clean and invalidate the entire cache.
30 */
31ENTRY(v4_flush_kern_cache_all)
1/*
2 * linux/arch/arm/mm/cache-v4.S
3 *
4 * Copyright (C) 1997-2002 Russell king
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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24ENTRY(v4_flush_user_cache_all)
25 /* FALLTHROUGH */
26/*
27 * flush_kern_cache_all()
28 *
29 * Clean and invalidate the entire cache.
30 */
31ENTRY(v4_flush_kern_cache_all)
32#ifdef CPU_CP15
32 mov r0, #0
33 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
34 mov pc, lr
33 mov r0, #0
34 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
35 mov pc, lr
36#else
37 /* FALLTHROUGH */
38#endif
35
36/*
37 * flush_user_cache_range(start, end, flags)
38 *
39 * Invalidate a range of cache entries in the specified
40 * address space.
41 *
42 * - start - start address (may not be aligned)
43 * - end - end address (exclusive, may not be aligned)
44 * - flags - vma_area_struct flags describing address space
45 */
46ENTRY(v4_flush_user_cache_range)
39
40/*
41 * flush_user_cache_range(start, end, flags)
42 *
43 * Invalidate a range of cache entries in the specified
44 * address space.
45 *
46 * - start - start address (may not be aligned)
47 * - end - end address (exclusive, may not be aligned)
48 * - flags - vma_area_struct flags describing address space
49 */
50ENTRY(v4_flush_user_cache_range)
51#ifdef CPU_CP15
47 mov ip, #0
48 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
49 mov pc, lr
52 mov ip, #0
53 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
54 mov pc, lr
55#else
56 /* FALLTHROUGH */
57#endif
50
51/*
52 * coherent_kern_range(start, end)
53 *
54 * Ensure coherency between the Icache and the Dcache in the
55 * region described by start. If you have non-snooping
56 * Harvard caches, you need to implement this function.
57 *

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103 * dma_flush_range(start, end)
104 *
105 * Clean and invalidate the specified virtual address range.
106 *
107 * - start - virtual start address
108 * - end - virtual end address
109 */
110ENTRY(v4_dma_flush_range)
58
59/*
60 * coherent_kern_range(start, end)
61 *
62 * Ensure coherency between the Icache and the Dcache in the
63 * region described by start. If you have non-snooping
64 * Harvard caches, you need to implement this function.
65 *

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111 * dma_flush_range(start, end)
112 *
113 * Clean and invalidate the specified virtual address range.
114 *
115 * - start - virtual start address
116 * - end - virtual end address
117 */
118ENTRY(v4_dma_flush_range)
119#ifdef CPU_CP15
111 mov r0, #0
112 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
120 mov r0, #0
121 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
122#endif
113 /* FALLTHROUGH */
114
115/*
116 * dma_clean_range(start, end)
117 *
118 * Clean (write back) the specified virtual address range.
119 *
120 * - start - virtual start address

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124
125/*
126 * dma_clean_range(start, end)
127 *
128 * Clean (write back) the specified virtual address range.
129 *
130 * - start - virtual start address

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