cache-uniphier.c (e82a82c19f4272ea5437cc76e5711b98e2ee6223) cache-uniphier.c (dd34b115666a1ccc69e3af52cc92c7410490f4fd)
1/*
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
2 * Copyright (C) 2015-2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of

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38/* operation registers */
39#define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */
40#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
41#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
42#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
43#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
44#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
45#define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of

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39/* operation registers */
40#define UNIPHIER_SSCOPE 0x244 /* Cache Operation Primitive Entry */
41#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
42#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
43#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
44#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
45#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
46#define UNIPHIER_SSCOQM 0x248 /* Cache Operation Queue Mode */
46#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
47#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
48#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
49#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
50#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
51#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
52#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
47#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
48#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
49#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
53#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
54#define UNIPHIER_SSCOQM_CE BIT(15) /* notify completion */
55#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
56#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
57#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
50#define UNIPHIER_SSCOQM_CE BIT(15) /* notify completion */
51#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
52#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
53#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
58#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
59#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
60#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
61#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
62#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
63#define UNIPHIER_SSCOQAD 0x24c /* Cache Operation Queue Address */
64#define UNIPHIER_SSCOQSZ 0x250 /* Cache Operation Queue Size */
54#define UNIPHIER_SSCOQAD 0x24c /* Cache Operation Queue Address */
55#define UNIPHIER_SSCOQSZ 0x250 /* Cache Operation Queue Size */
65#define UNIPHIER_SSCOQMASK 0x254 /* Cache Operation Queue Address Mask */
66#define UNIPHIER_SSCOQWN 0x258 /* Cache Operation Queue Way Number */
67#define UNIPHIER_SSCOPPQSEF 0x25c /* Cache Operation Queue Set Complete*/
68#define UNIPHIER_SSCOPPQSEF_FE BIT(1)
69#define UNIPHIER_SSCOPPQSEF_OE BIT(0)
70#define UNIPHIER_SSCOLPQS 0x260 /* Cache Operation Queue Status */
71#define UNIPHIER_SSCOLPQS_EF BIT(2)
72#define UNIPHIER_SSCOLPQS_EST BIT(1)
73#define UNIPHIER_SSCOLPQS_QST BIT(0)
74
56#define UNIPHIER_SSCOPPQSEF 0x25c /* Cache Operation Queue Set Complete*/
57#define UNIPHIER_SSCOPPQSEF_FE BIT(1)
58#define UNIPHIER_SSCOPPQSEF_OE BIT(0)
59#define UNIPHIER_SSCOLPQS 0x260 /* Cache Operation Queue Status */
60#define UNIPHIER_SSCOLPQS_EF BIT(2)
61#define UNIPHIER_SSCOLPQS_EST BIT(1)
62#define UNIPHIER_SSCOLPQS_QST BIT(0)
63
75/* Is the touch/pre-fetch destination specified by ways? */
76#define UNIPHIER_SSCOQM_TID_IS_WAY(op) \
77 ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)
78/* Is the operation region specified by address range? */
79#define UNIPHIER_SSCOQM_S_IS_RANGE(op) \
80 ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
81
82/**
83 * uniphier_cache_data - UniPhier outer cache specific data
84 *
85 * @ctrl_base: virtual base address of control registers

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173 writel_relaxed(UNIPHIER_SSCOQM_CE | operation,
174 data->op_base + UNIPHIER_SSCOQM);
175
176 /* set address range if needed */
177 if (likely(UNIPHIER_SSCOQM_S_IS_RANGE(operation))) {
178 writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD);
179 writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ);
180 }
64/* Is the operation region specified by address range? */
65#define UNIPHIER_SSCOQM_S_IS_RANGE(op) \
66 ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
67
68/**
69 * uniphier_cache_data - UniPhier outer cache specific data
70 *
71 * @ctrl_base: virtual base address of control registers

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159 writel_relaxed(UNIPHIER_SSCOQM_CE | operation,
160 data->op_base + UNIPHIER_SSCOQM);
161
162 /* set address range if needed */
163 if (likely(UNIPHIER_SSCOQM_S_IS_RANGE(operation))) {
164 writel_relaxed(start, data->op_base + UNIPHIER_SSCOQAD);
165 writel_relaxed(size, data->op_base + UNIPHIER_SSCOQSZ);
166 }
181
182 /* set target ways if needed */
183 if (unlikely(UNIPHIER_SSCOQM_TID_IS_WAY(operation)))
184 writel_relaxed(data->way_locked_mask,
185 data->op_base + UNIPHIER_SSCOQWN);
186 } while (unlikely(readl_relaxed(data->op_base + UNIPHIER_SSCOPPQSEF) &
187 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
188
189 /* wait until the operation is completed */
190 while (likely(readl_relaxed(data->op_base + UNIPHIER_SSCOLPQS) !=
191 UNIPHIER_SSCOLPQS_EF))
192 cpu_relax();
193

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333static void uniphier_cache_sync(void)
334{
335 struct uniphier_cache_data *data;
336
337 list_for_each_entry(data, &uniphier_cache_list, list)
338 __uniphier_cache_sync(data);
339}
340
167 } while (unlikely(readl_relaxed(data->op_base + UNIPHIER_SSCOPPQSEF) &
168 (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
169
170 /* wait until the operation is completed */
171 while (likely(readl_relaxed(data->op_base + UNIPHIER_SSCOLPQS) !=
172 UNIPHIER_SSCOLPQS_EF))
173 cpu_relax();
174

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314static void uniphier_cache_sync(void)
315{
316 struct uniphier_cache_data *data;
317
318 list_for_each_entry(data, &uniphier_cache_list, list)
319 __uniphier_cache_sync(data);
320}
321
341int __init uniphier_cache_l2_is_enabled(void)
342{
343 struct uniphier_cache_data *data;
344
345 data = list_first_entry_or_null(&uniphier_cache_list,
346 struct uniphier_cache_data, list);
347 if (!data)
348 return 0;
349
350 return !!(readl_relaxed(data->ctrl_base + UNIPHIER_SSCC) &
351 UNIPHIER_SSCC_ON);
352}
353
354void __init uniphier_cache_l2_touch_range(unsigned long start,
355 unsigned long end)
356{
357 struct uniphier_cache_data *data;
358
359 data = list_first_entry_or_null(&uniphier_cache_list,
360 struct uniphier_cache_data, list);
361 if (data)
362 __uniphier_cache_maint_range(data, start, end,
363 UNIPHIER_SSCOQM_TID_WAY |
364 UNIPHIER_SSCOQM_CM_TOUCH);
365}
366
367void __init uniphier_cache_l2_set_locked_ways(u32 way_mask)
368{
369 struct uniphier_cache_data *data;
370
371 data = list_first_entry_or_null(&uniphier_cache_list,
372 struct uniphier_cache_data, list);
373 if (data)
374 __uniphier_cache_set_locked_ways(data, way_mask);
375}
376
377static const struct of_device_id uniphier_cache_match[] __initconst = {
322static const struct of_device_id uniphier_cache_match[] __initconst = {
378 {
379 .compatible = "socionext,uniphier-system-cache",
380 },
323 { .compatible = "socionext,uniphier-system-cache" },
381 { /* sentinel */ }
382};
383
384static int __init __uniphier_cache_init(struct device_node *np,
385 unsigned int *cache_level)
386{
387 struct uniphier_cache_data *data;
388 u32 level, cache_size;

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325};
326
327static int __init __uniphier_cache_init(struct device_node *np,
328 unsigned int *cache_level)
329{
330 struct uniphier_cache_data *data;
331 u32 level, cache_size;

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