| abort-ev6.S (d585a021c0b10b0477d6b608c53e1feb8cde0507) | abort-ev6.S (26584853a44c58f3d6ac7360d697a2ddcd1a3efa) |
|---|---|
| 1#include <linux/linkage.h> 2#include <asm/assembler.h> 3#include "abort-macro.S" 4/* 5 * Function: v6_early_abort 6 * 7 * Params : r2 = address of aborted instruction 8 * : r3 = saved SPSR --- 23 unchanged lines hidden (view full) --- 32 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). 33 * The test below covers all the write situations, including Java bytecodes 34 */ 35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR 36 tst r3, #PSR_J_BIT @ Java? 37 movne pc, lr 38 do_thumb_abort 39 ldreq r3, [r2] @ read aborted ARM instruction | 1#include <linux/linkage.h> 2#include <asm/assembler.h> 3#include "abort-macro.S" 4/* 5 * Function: v6_early_abort 6 * 7 * Params : r2 = address of aborted instruction 8 * : r3 = saved SPSR --- 23 unchanged lines hidden (view full) --- 32 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). 33 * The test below covers all the write situations, including Java bytecodes 34 */ 35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR 36 tst r3, #PSR_J_BIT @ Java? 37 movne pc, lr 38 do_thumb_abort 39 ldreq r3, [r2] @ read aborted ARM instruction |
| 40#ifdef CONFIG_CPU_ENDIAN_BE8 41 reveq r3, r3 42#endif |
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| 40 do_ldrd_abort 41 tst r3, #1 << 20 @ L = 0 -> write 42 orreq r1, r1, #1 << 11 @ yes. 43 mov pc, lr 44 45 | 43 do_ldrd_abort 44 tst r3, #1 << 20 @ L = 0 -> write 45 orreq r1, r1, #1 << 11 @ yes. 46 mov pc, lr 47 48 |