| Kconfig (6ec9dc323b0fd4b83e6da64acc871f74508c0077) | Kconfig (ba364fc752daeded072a5ef31e43b84cb1f9e5fd) |
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| 1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI --- 840 unchanged lines hidden (view full) --- 849config OUTER_CACHE_SYNC 850 bool 851 help 852 The outer cache has a outer_cache_fns.sync function pointer 853 that can be used to drain the write buffer of the outer cache. 854 855config CACHE_FEROCEON_L2 856 bool "Enable the Feroceon L2 cache controller" | 1comment "Processor Type" 2 3# Select CPU types depending on the architecture selected. This selects 4# which CPUs we support in the kernel image, and the compiler instruction 5# optimiser behaviour. 6 7# ARM7TDMI 8config CPU_ARM7TDMI --- 840 unchanged lines hidden (view full) --- 849config OUTER_CACHE_SYNC 850 bool 851 help 852 The outer cache has a outer_cache_fns.sync function pointer 853 that can be used to drain the write buffer of the outer cache. 854 855config CACHE_FEROCEON_L2 856 bool "Enable the Feroceon L2 cache controller" |
| 857 depends on ARCH_KIRKWOOD || ARCH_MV78XX0 || ARCH_MVEBU | 857 depends on ARCH_MV78XX0 || ARCH_MVEBU |
| 858 default y 859 select OUTER_CACHE 860 help 861 This option enables the Feroceon L2 cache controller. 862 863config CACHE_FEROCEON_L2_WRITETHROUGH 864 bool "Force Feroceon L2 cache write through" 865 depends on CACHE_FEROCEON_L2 --- 18 unchanged lines hidden (view full) --- 884config CACHE_L2X0 885 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 886 default MIGHT_HAVE_CACHE_L2X0 887 select OUTER_CACHE 888 select OUTER_CACHE_SYNC 889 help 890 This option enables the L2x0 PrimeCell. 891 | 858 default y 859 select OUTER_CACHE 860 help 861 This option enables the Feroceon L2 cache controller. 862 863config CACHE_FEROCEON_L2_WRITETHROUGH 864 bool "Force Feroceon L2 cache write through" 865 depends on CACHE_FEROCEON_L2 --- 18 unchanged lines hidden (view full) --- 884config CACHE_L2X0 885 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 886 default MIGHT_HAVE_CACHE_L2X0 887 select OUTER_CACHE 888 select OUTER_CACHE_SYNC 889 help 890 This option enables the L2x0 PrimeCell. 891 |
| 892if CACHE_L2X0 893 | |
| 894config CACHE_PL310 895 bool | 892config CACHE_PL310 893 bool |
| 894 depends on CACHE_L2X0 |
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| 896 default y if CPU_V7 && !(CPU_V6 || CPU_V6K) 897 help 898 This option enables optimisations for the PL310 cache 899 controller. 900 901config PL310_ERRATA_588369 902 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" | 895 default y if CPU_V7 && !(CPU_V6 || CPU_V6K) 896 help 897 This option enables optimisations for the PL310 cache 898 controller. 899 900config PL310_ERRATA_588369 901 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" |
| 902 depends on CACHE_L2X0 |
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| 903 help 904 The PL310 L2 cache controller implements three types of Clean & 905 Invalidate maintenance operations: by Physical Address 906 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 907 They are architecturally defined to behave as the execution of a 908 clean operation followed immediately by an invalidate operation, 909 both performing to the same memory location. This functionality 910 is not correctly implemented in PL310 as clean lines are not 911 invalidated as a result of these operations. 912 913config PL310_ERRATA_727915 914 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" | 903 help 904 The PL310 L2 cache controller implements three types of Clean & 905 Invalidate maintenance operations: by Physical Address 906 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). 907 They are architecturally defined to behave as the execution of a 908 clean operation followed immediately by an invalidate operation, 909 both performing to the same memory location. This functionality 910 is not correctly implemented in PL310 as clean lines are not 911 invalidated as a result of these operations. 912 913config PL310_ERRATA_727915 914 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" |
| 915 depends on CACHE_L2X0 |
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| 915 help 916 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 917 operation (offset 0x7FC). This operation runs in background so that 918 PL310 can handle normal accesses while it is in progress. Under very 919 rare circumstances, due to this erratum, write data can be lost when 920 PL310 treats a cacheable write transaction during a Clean & 921 Invalidate by Way operation. 922 923config PL310_ERRATA_753970 924 bool "PL310 errata: cache sync operation may be faulty" | 916 help 917 PL310 implements the Clean & Invalidate by Way L2 cache maintenance 918 operation (offset 0x7FC). This operation runs in background so that 919 PL310 can handle normal accesses while it is in progress. Under very 920 rare circumstances, due to this erratum, write data can be lost when 921 PL310 treats a cacheable write transaction during a Clean & 922 Invalidate by Way operation. 923 924config PL310_ERRATA_753970 925 bool "PL310 errata: cache sync operation may be faulty" |
| 926 depends on CACHE_PL310 |
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| 925 help 926 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 927 928 Under some condition the effect of cache sync operation on 929 the store buffer still remains when the operation completes. 930 This means that the store buffer is always asked to drain and 931 this prevents it from merging any further writes. The workaround 932 is to replace the normal offset of cache sync operation (0x730) 933 by another offset targeting an unmapped PL310 register 0x740. 934 This has the same effect as the cache sync operation: store buffer 935 drain and waiting for all buffers empty. 936 937config PL310_ERRATA_769419 938 bool "PL310 errata: no automatic Store Buffer drain" | 927 help 928 This option enables the workaround for the 753970 PL310 (r3p0) erratum. 929 930 Under some condition the effect of cache sync operation on 931 the store buffer still remains when the operation completes. 932 This means that the store buffer is always asked to drain and 933 this prevents it from merging any further writes. The workaround 934 is to replace the normal offset of cache sync operation (0x730) 935 by another offset targeting an unmapped PL310 register 0x740. 936 This has the same effect as the cache sync operation: store buffer 937 drain and waiting for all buffers empty. 938 939config PL310_ERRATA_769419 940 bool "PL310 errata: no automatic Store Buffer drain" |
| 941 depends on CACHE_L2X0 |
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| 939 help 940 On revisions of the PL310 prior to r3p2, the Store Buffer does 941 not automatically drain. This can cause normal, non-cacheable 942 writes to be retained when the memory system is idle, leading 943 to suboptimal I/O performance for drivers using coherent DMA. 944 This option adds a write barrier to the cpu_idle loop so that, 945 on systems with an outer cache, the store buffer is drained 946 explicitly. 947 | 942 help 943 On revisions of the PL310 prior to r3p2, the Store Buffer does 944 not automatically drain. This can cause normal, non-cacheable 945 writes to be retained when the memory system is idle, leading 946 to suboptimal I/O performance for drivers using coherent DMA. 947 This option adds a write barrier to the cpu_idle loop so that, 948 on systems with an outer cache, the store buffer is drained 949 explicitly. 950 |
| 948endif 949 | |
| 950config CACHE_TAUROS2 951 bool "Enable the Tauros2 L2 cache controller" 952 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) 953 default y 954 select OUTER_CACHE 955 help 956 This option enables the Tauros2 L2 cache controller (as 957 found on PJ1/PJ4). --- 52 unchanged lines hidden --- | 951config CACHE_TAUROS2 952 bool "Enable the Tauros2 L2 cache controller" 953 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) 954 default y 955 select OUTER_CACHE 956 help 957 This option enables the Tauros2 L2 cache controller (as 958 found on PJ1/PJ4). --- 52 unchanged lines hidden --- |