common.c (96790f0a283976bc59f68657237293fe97b02334) common.c (889faa88142801ee6bec2de2b8fb4c606076d52f)
1/*
2 * This file contains common code that is intended to be used across
3 * boards so that it's not replicated.
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and

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41void __iomem *zynq_scu_base;
42
43static struct of_device_id zynq_of_bus_ids[] __initdata = {
44 { .compatible = "simple-bus", },
45 {}
46};
47
48/**
1/*
2 * This file contains common code that is intended to be used across
3 * boards so that it's not replicated.
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and

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41void __iomem *zynq_scu_base;
42
43static struct of_device_id zynq_of_bus_ids[] __initdata = {
44 { .compatible = "simple-bus", },
45 {}
46};
47
48/**
49 * xilinx_init_machine() - System specific initialization, intended to be
50 * called from board specific initialization.
49 * zynq_init_machine - System specific initialization, intended to be
50 * called from board specific initialization.
51 */
51 */
52static void __init xilinx_init_machine(void)
52static void __init zynq_init_machine(void)
53{
54 /*
55 * 64KB way size, 8-way associativity, parity disabled
56 */
57 l2x0_of_init(0x02060000, 0xF0F0FFFF);
58
59 of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
60}
61
53{
54 /*
55 * 64KB way size, 8-way associativity, parity disabled
56 */
57 l2x0_of_init(0x02060000, 0xF0F0FFFF);
58
59 of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
60}
61
62static void __init xilinx_zynq_timer_init(void)
62static void __init zynq_timer_init(void)
63{
64 zynq_slcr_init();
65 clocksource_of_init();
66}
67
68static struct map_desc zynq_cortex_a9_scu_map __initdata = {
69 .length = SZ_256,
70 .type = MT_DEVICE,

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79 /* Expected address is in vmalloc area that's why simple assign here */
80 zynq_cortex_a9_scu_map.virtual = base;
81 iotable_init(&zynq_cortex_a9_scu_map, 1);
82 zynq_scu_base = (void __iomem *)base;
83 BUG_ON(!zynq_scu_base);
84}
85
86/**
63{
64 zynq_slcr_init();
65 clocksource_of_init();
66}
67
68static struct map_desc zynq_cortex_a9_scu_map __initdata = {
69 .length = SZ_256,
70 .type = MT_DEVICE,

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79 /* Expected address is in vmalloc area that's why simple assign here */
80 zynq_cortex_a9_scu_map.virtual = base;
81 iotable_init(&zynq_cortex_a9_scu_map, 1);
82 zynq_scu_base = (void __iomem *)base;
83 BUG_ON(!zynq_scu_base);
84}
85
86/**
87 * xilinx_map_io() - Create memory mappings needed for early I/O.
87 * zynq_map_io - Create memory mappings needed for early I/O.
88 */
88 */
89static void __init xilinx_map_io(void)
89static void __init zynq_map_io(void)
90{
91 debug_ll_io_init();
92 zynq_scu_map_io();
93}
94
95static void zynq_system_reset(char mode, const char *cmd)
96{
97 zynq_slcr_system_reset();
98}
99
90{
91 debug_ll_io_init();
92 zynq_scu_map_io();
93}
94
95static void zynq_system_reset(char mode, const char *cmd)
96{
97 zynq_slcr_system_reset();
98}
99
100static const char *xilinx_dt_match[] = {
100static const char * const zynq_dt_match[] = {
101 "xlnx,zynq-zc702",
102 "xlnx,zynq-7000",
103 NULL
104};
105
106MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
101 "xlnx,zynq-zc702",
102 "xlnx,zynq-7000",
103 NULL
104};
105
106MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
107 .map_io = xilinx_map_io,
107 .map_io = zynq_map_io,
108 .init_irq = irqchip_init,
108 .init_irq = irqchip_init,
109 .init_machine = xilinx_init_machine,
110 .init_time = xilinx_zynq_timer_init,
111 .dt_compat = xilinx_dt_match,
109 .init_machine = zynq_init_machine,
110 .init_time = zynq_timer_init,
111 .dt_compat = zynq_dt_match,
112 .restart = zynq_system_reset,
113MACHINE_END
112 .restart = zynq_system_reset,
113MACHINE_END