| sleep.h (cb54b53adae70701bdd77d848cea4b9b39b61cf9) | sleep.h (e7a932b1961c3936c7ae5b8d1628f39dc50a746d) |
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| 1/* 2 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 27 unchanged lines hidden (view full) --- 36#define PMC_SCRATCH41 0x140 37 38#ifdef CONFIG_ARCH_TEGRA_2x_SOC 39#define CPU_RESETTABLE 2 40#define CPU_RESETTABLE_SOON 1 41#define CPU_NOT_RESETTABLE 0 42#endif 43 | 1/* 2 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 27 unchanged lines hidden (view full) --- 36#define PMC_SCRATCH41 0x140 37 38#ifdef CONFIG_ARCH_TEGRA_2x_SOC 39#define CPU_RESETTABLE 2 40#define CPU_RESETTABLE_SOON 1 41#define CPU_NOT_RESETTABLE 0 42#endif 43 |
| 44/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */ 45#define TEGRA_FLUSH_CACHE_LOUIS 0 46#define TEGRA_FLUSH_CACHE_ALL 1 47 |
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| 44#ifdef __ASSEMBLY__ | 48#ifdef __ASSEMBLY__ |
| 49/* waits until the microsecond counter (base) is > rn */ 50.macro wait_until, rn, base, tmp 51 add \rn, \rn, #1 521001: ldr \tmp, [\base] 53 cmp \tmp, \rn 54 bmi 1001b 55.endm 56 |
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| 45/* returns the offset of the flow controller halt register for a cpu */ 46.macro cpu_to_halt_reg rd, rcpu 47 cmp \rcpu, #0 48 subne \rd, \rcpu, #1 49 movne \rd, \rd, lsl #3 50 addne \rd, \rd, #0x14 51 moveq \rd, #0 52.endm --- 86 unchanged lines hidden (view full) --- 139.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 140.endm 141#endif /* CONFIG_CACHE_L2X0 */ 142#else 143void tegra_pen_lock(void); 144void tegra_pen_unlock(void); 145void tegra_resume(void); 146int tegra_sleep_cpu_finish(unsigned long); | 57/* returns the offset of the flow controller halt register for a cpu */ 58.macro cpu_to_halt_reg rd, rcpu 59 cmp \rcpu, #0 60 subne \rd, \rcpu, #1 61 movne \rd, \rd, lsl #3 62 addne \rd, \rd, #0x14 63 moveq \rd, #0 64.endm --- 86 unchanged lines hidden (view full) --- 151.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs 152.endm 153#endif /* CONFIG_CACHE_L2X0 */ 154#else 155void tegra_pen_lock(void); 156void tegra_pen_unlock(void); 157void tegra_resume(void); 158int tegra_sleep_cpu_finish(unsigned long); |
| 147void tegra_disable_clean_inv_dcache(void); | 159void tegra_disable_clean_inv_dcache(u32 flag); |
| 148 149#ifdef CONFIG_HOTPLUG_CPU 150void tegra20_hotplug_shutdown(void); 151void tegra30_hotplug_shutdown(void); 152void tegra_hotplug_init(void); 153#else 154static inline void tegra_hotplug_init(void) {} 155#endif --- 17 unchanged lines hidden --- | 160 161#ifdef CONFIG_HOTPLUG_CPU 162void tegra20_hotplug_shutdown(void); 163void tegra30_hotplug_shutdown(void); 164void tegra_hotplug_init(void); 165#else 166static inline void tegra_hotplug_init(void) {} 167#endif --- 17 unchanged lines hidden --- |