sleep.S (cb54b53adae70701bdd77d848cea4b9b39b61cf9) sleep.S (e7a932b1961c3936c7ae5b8d1628f39dc50a746d)
1/*
2 * arch/arm/mach-tegra/sleep.S
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
6 *
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>

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51
52 /* Disable the D-cache */
53 mrc p15, 0, r2, c1, c0, 0
54 bic r2, r2, #CR_C
55 mcr p15, 0, r2, c1, c0, 0
56 isb
57
58 /* Flush the D-cache */
1/*
2 * arch/arm/mach-tegra/sleep.S
3 *
4 * Copyright (c) 2010-2011, NVIDIA Corporation.
5 * Copyright (c) 2011, Google, Inc.
6 *
7 * Author: Colin Cross <ccross@android.com>
8 * Gary King <gking@nvidia.com>

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51
52 /* Disable the D-cache */
53 mrc p15, 0, r2, c1, c0, 0
54 bic r2, r2, #CR_C
55 mcr p15, 0, r2, c1, c0, 0
56 isb
57
58 /* Flush the D-cache */
59 bl v7_flush_dcache_louis
59 cmp r0, #TEGRA_FLUSH_CACHE_ALL
60 blne v7_flush_dcache_louis
61 bleq v7_flush_dcache_all
60
61 /* Trun off coherency */
62 exit_smp r4, r5
63
64 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
65ENDPROC(tegra_disable_clean_inv_dcache)
66#endif
67
68#ifdef CONFIG_PM_SLEEP
69/*
62
63 /* Trun off coherency */
64 exit_smp r4, r5
65
66 ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
67ENDPROC(tegra_disable_clean_inv_dcache)
68#endif
69
70#ifdef CONFIG_PM_SLEEP
71/*
72 * tegra_init_l2_for_a15
73 *
74 * set up the correct L2 cache data RAM latency
75 */
76ENTRY(tegra_init_l2_for_a15)
77 mrc p15, 0, r0, c0, c0, 5
78 ubfx r0, r0, #8, #4
79 tst r0, #1 @ only need for cluster 0
80 bne _exit_init_l2_a15
81
82 mrc p15, 0x1, r0, c9, c0, 2
83 and r0, r0, #7
84 cmp r0, #2
85 bicne r0, r0, #7
86 orrne r0, r0, #2
87 mcrne p15, 0x1, r0, c9, c0, 2
88_exit_init_l2_a15:
89
90 mov pc, lr
91ENDPROC(tegra_init_l2_for_a15)
92
93/*
70 * tegra_sleep_cpu_finish(unsigned long v2p)
71 *
72 * enters suspend in LP2 by turning off the mmu and jumping to
73 * tegra?_tear_down_cpu
74 */
75ENTRY(tegra_sleep_cpu_finish)
94 * tegra_sleep_cpu_finish(unsigned long v2p)
95 *
96 * enters suspend in LP2 by turning off the mmu and jumping to
97 * tegra?_tear_down_cpu
98 */
99ENTRY(tegra_sleep_cpu_finish)
100 mov r4, r0
76 /* Flush and disable the L1 data cache */
101 /* Flush and disable the L1 data cache */
102 mov r0, #TEGRA_FLUSH_CACHE_ALL
77 bl tegra_disable_clean_inv_dcache
78
103 bl tegra_disable_clean_inv_dcache
104
105 mov r0, r4
79 mov32 r6, tegra_tear_down_cpu
80 ldr r1, [r6]
81 add r1, r1, r0
82
83 mov32 r3, tegra_shut_off_mmu
84 add r3, r3, r0
85 mov r0, r1
86

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102 movw r2, #CR_I | CR_Z | CR_C | CR_M
103 bic r3, r3, r2
104 dsb
105 mcr p15, 0, r3, c1, c0, 0
106 isb
107#ifdef CONFIG_CACHE_L2X0
108 /* Disable L2 cache */
109 check_cpu_part_num 0xc09, r9, r10
106 mov32 r6, tegra_tear_down_cpu
107 ldr r1, [r6]
108 add r1, r1, r0
109
110 mov32 r3, tegra_shut_off_mmu
111 add r3, r3, r0
112 mov r0, r1
113

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129 movw r2, #CR_I | CR_Z | CR_C | CR_M
130 bic r3, r3, r2
131 dsb
132 mcr p15, 0, r3, c1, c0, 0
133 isb
134#ifdef CONFIG_CACHE_L2X0
135 /* Disable L2 cache */
136 check_cpu_part_num 0xc09, r9, r10
110 movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
111 movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
112 moveq r5, #0
113 streq r5, [r4, #L2X0_CTRL]
137 movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
138 movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
139 moveq r3, #0
140 streq r3, [r2, #L2X0_CTRL]
114#endif
115 mov pc, r0
116ENDPROC(tegra_shut_off_mmu)
117 .popsection
118
119/*
120 * tegra_switch_cpu_to_pllp
121 *

--- 13 unchanged lines hidden --- 		141#endif
142 mov pc, r0
143ENDPROC(tegra_shut_off_mmu)
144 .popsection
145
146/*
147 * tegra_switch_cpu_to_pllp
148 *

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