| sleep.S (9a64e8e0ace51b309fdcff4b4754b3649250382a) | sleep.S (d0a533b18235d36206b9b422efadb7cee444dfdb) |
|---|---|
| 1/* 2 * SA11x0 Assembler Sleep/WakeUp Management Routines 3 * 4 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License. 8 * --- 24 unchanged lines hidden (view full) --- 33 @ disable clock switching 34 mcr p15, 0, r1, c15, c2, 2 35 36 ldr r6, =MDREFR 37 ldr r4, [r6] 38 orr r4, r4, #MDREFR_K1DB2 39 ldr r5, =PPCR 40 | 1/* 2 * SA11x0 Assembler Sleep/WakeUp Management Routines 3 * 4 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License. 8 * --- 24 unchanged lines hidden (view full) --- 33 @ disable clock switching 34 mcr p15, 0, r1, c15, c2, 2 35 36 ldr r6, =MDREFR 37 ldr r4, [r6] 38 orr r4, r4, #MDREFR_K1DB2 39 ldr r5, =PPCR 40 |
| 41 @ Pre-load __udelay into the I-cache | 41 @ Pre-load __loop_udelay into the I-cache |
| 42 mov r0, #1 | 42 mov r0, #1 |
| 43 bl __udelay | 43 bl __loop_udelay |
| 44 mov r0, r0 45 46 @ The following must all exist in a single cache line to 47 @ avoid accessing memory until this sequence is complete, 48 @ otherwise we occasionally hang. 49 50 @ Adjust memory timing before lowering CPU clock 51 str r4, [r6] 52 53 @ delay 90us and set CPU PLL to lowest speed 54 @ fixes resume problem on high speed SA1110 55 mov r0, #90 | 44 mov r0, r0 45 46 @ The following must all exist in a single cache line to 47 @ avoid accessing memory until this sequence is complete, 48 @ otherwise we occasionally hang. 49 50 @ Adjust memory timing before lowering CPU clock 51 str r4, [r6] 52 53 @ delay 90us and set CPU PLL to lowest speed 54 @ fixes resume problem on high speed SA1110 55 mov r0, #90 |
| 56 bl __udelay | 56 bl __loop_udelay |
| 57 mov r1, #0 58 str r1, [r5] 59 mov r0, #90 | 57 mov r1, #0 58 str r1, [r5] 59 mov r0, #90 |
| 60 bl __udelay | 60 bl __loop_udelay |
| 61 62 /* 63 * SA1110 SDRAM controller workaround. register values: 64 * 65 * r0 = &MSC0 66 * r1 = &MSC1 67 * r2 = &MSC2 68 * r3 = MSC0 value --- 75 unchanged lines hidden --- | 61 62 /* 63 * SA1110 SDRAM controller workaround. register values: 64 * 65 * r0 = &MSC0 66 * r1 = &MSC1 67 * r2 = &MSC2 68 * r3 = MSC0 value --- 75 unchanged lines hidden --- |