pxa3xx.c (85e9ca333d03fbd56b9e123c8456f0d98e20faad) pxa3xx.c (04fef228fb00dd79475a2313f4ba73b4fbfe2faa)
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/sysdev.h>
24
25#include <asm/hardware.h>
26#include <asm/arch/pxa3xx-regs.h>
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/sysdev.h>
24
25#include <asm/hardware.h>
26#include <asm/arch/pxa3xx-regs.h>
27#include <asm/arch/reset.h>
27#include <asm/arch/ohci.h>
28#include <asm/arch/pm.h>
29#include <asm/arch/dma.h>
30#include <asm/arch/ssp.h>
31
32#include "generic.h"
33#include "devices.h"
34#include "clock.h"

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104 acsr = ACSR;
105
106 smcfs = (acsr >> 23) & 0x7;
107 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
108
109 return (clk / 10000);
110}
111
28#include <asm/arch/ohci.h>
29#include <asm/arch/pm.h>
30#include <asm/arch/dma.h>
31#include <asm/arch/ssp.h>
32
33#include "generic.h"
34#include "devices.h"
35#include "clock.h"

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105 acsr = ACSR;
106
107 smcfs = (acsr >> 23) & 0x7;
108 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
109
110 return (clk / 10000);
111}
112
113void pxa3xx_clear_reset_status(unsigned int mask)
114{
115 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
116 ARSR = mask;
117}
118
112/*
113 * Return the current AC97 clock frequency.
114 */
115static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
116{
117 unsigned long rate = 312000000;
118 unsigned long ac97_div;
119

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527 },
528};
529
530static int __init pxa3xx_init(void)
531{
532 int i, ret = 0;
533
534 if (cpu_is_pxa3xx()) {
119/*
120 * Return the current AC97 clock frequency.
121 */
122static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
123{
124 unsigned long rate = 312000000;
125 unsigned long ac97_div;
126

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534 },
535};
536
537static int __init pxa3xx_init(void)
538{
539 int i, ret = 0;
540
541 if (cpu_is_pxa3xx()) {
542
543 reset_status = ARSR;
544
535 /*
536 * clear RDH bit every time after reset
537 *
538 * Note: the last 3 bits DxS are write-1-to-clear so carefully
539 * preserve them here in case they will be referenced later
540 */
541 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
542

--- 20 unchanged lines hidden --- 		545 /*
546 * clear RDH bit every time after reset
547 *
548 * Note: the last 3 bits DxS are write-1-to-clear so carefully
549 * preserve them here in case they will be referenced later
550 */
551 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
552

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