pxa3xx.c (5cbee140a28c2746449ae31e85738043ae4da927) pxa3xx.c (293b2da1b61136813fc2764f43304c66ff8040e9)
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h>
20#include <linux/irq.h>
21#include <linux/io.h>
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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14 */
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/syscore_ops.h>
24#include <linux/i2c/pxa-i2c.h>
25
26#include <asm/mach/map.h>
27#include <asm/suspend.h>
28#include <mach/hardware.h>
29#include <mach/pxa3xx-regs.h>
30#include <mach/reset.h>
22#include <linux/syscore_ops.h>
23#include <linux/i2c/pxa-i2c.h>
24
25#include <asm/mach/map.h>
26#include <asm/suspend.h>
27#include <mach/hardware.h>
28#include <mach/pxa3xx-regs.h>
29#include <mach/reset.h>
31#include <mach/ohci.h>
30#include <linux/platform_data/usb-ohci-pxa27x.h>
32#include <mach/pm.h>
33#include <mach/dma.h>
34#include <mach/smemc.h>
35#include <mach/irqs.h>
36
37#include "generic.h"
38#include "devices.h"
39#include "clock.h"
40
41#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
42#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
43
31#include <mach/pm.h>
32#include <mach/dma.h>
33#include <mach/smemc.h>
34#include <mach/irqs.h>
35
36#include "generic.h"
37#include "devices.h"
38#include "clock.h"
39
40#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
41#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
42
44extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
45
46static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
47static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
48static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
49static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
50static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
51static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
52static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
53static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);

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380 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
381 handle_edge_irq);
382 set_irq_flags(irq, IRQF_VALID);
383 }
384
385 pxa_ext_wakeup_chip.irq_set_wake = fn;
386}
387
43static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
44static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
45static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
46static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
47static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
48static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
49static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
50static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);

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377 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
378 handle_edge_irq);
379 set_irq_flags(irq, IRQF_VALID);
380 }
381
382 pxa_ext_wakeup_chip.irq_set_wake = fn;
383}
384
388static void __init __pxa3xx_init_irq(void)
385void __init pxa3xx_init_irq(void)
389{
390 /* enable CP6 access */
391 u32 value;
392 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
393 value |= (1 << 6);
394 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
395
386{
387 /* enable CP6 access */
388 u32 value;
389 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
390 value |= (1 << 6);
391 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
392
393 pxa_init_irq(56, pxa3xx_set_wake);
396 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
397}
398
394 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
395}
396
399void __init pxa3xx_init_irq(void)
400{
401 __pxa3xx_init_irq();
402 pxa_init_irq(56, pxa3xx_set_wake);
403}
404
405#ifdef CONFIG_OF
406void __init pxa3xx_dt_init_irq(void)
407{
408 __pxa3xx_init_irq();
409 pxa_dt_irq_init(pxa3xx_set_wake);
410}
411#endif /* CONFIG_OF */
412
413static struct map_desc pxa3xx_io_desc[] __initdata = {
414 { /* Mem Ctl */
415 .virtual = (unsigned long)SMEMC_VIRT,
416 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
417 .length = 0x00200000,
418 .type = MT_DEVICE
419 }
420};

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477 return ret;
478
479 pxa3xx_init_pm();
480
481 register_syscore_ops(&pxa_irq_syscore_ops);
482 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
483 register_syscore_ops(&pxa3xx_clock_syscore_ops);
484
397static struct map_desc pxa3xx_io_desc[] __initdata = {
398 { /* Mem Ctl */
399 .virtual = (unsigned long)SMEMC_VIRT,
400 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
401 .length = 0x00200000,
402 .type = MT_DEVICE
403 }
404};

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461 return ret;
462
463 pxa3xx_init_pm();
464
465 register_syscore_ops(&pxa_irq_syscore_ops);
466 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
467 register_syscore_ops(&pxa3xx_clock_syscore_ops);
468
485 if (!of_have_populated_dt())
486 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
469 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
487 }
488
489 return ret;
490}
491
492postcore_initcall(pxa3xx_init);
470 }
471
472 return ret;
473}
474
475postcore_initcall(pxa3xx_init);