pxa27x.c (c016550490687c6bdbcdf06c7b4d874b6c7c6e4e) pxa27x.c (16dfdbf038706c12c56f327d14c6b901edc376a3)
1/*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.

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167 */
168};
169
170#ifdef CONFIG_PM
171
172#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
173#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
174
1/*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.

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167 */
168};
169
170#ifdef CONFIG_PM
171
172#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
173#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
174
175#define RESTORE_GPLEVEL(n) do { \
176 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
177 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
178} while (0)
179
180/*
181 * List of global PXA peripheral registers to preserve.
182 * More ones like CP and general purpose register values are preserved
183 * with the stack pointer in sleep.S.
184 */
185enum { SLEEP_SAVE_START = 0,
186
175/*
176 * List of global PXA peripheral registers to preserve.
177 * More ones like CP and general purpose register values are preserved
178 * with the stack pointer in sleep.S.
179 */
180enum { SLEEP_SAVE_START = 0,
181
187 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
188 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
189 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
190 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
191 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
192
193 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
194 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
195 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
196 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
197
198 SLEEP_SAVE_PSTR,

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203 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
204 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
205
206 SLEEP_SAVE_SIZE
207};
208
209void pxa27x_cpu_pm_save(unsigned long *sleep_save)
210{
182 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
183
184 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
185 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
186 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
187 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
188
189 SLEEP_SAVE_PSTR,

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194 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
195 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
196
197 SLEEP_SAVE_SIZE
198};
199
200void pxa27x_cpu_pm_save(unsigned long *sleep_save)
201{
211 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
212 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
213 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
214 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
215 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
216
217 SAVE(GAFR0_L); SAVE(GAFR0_U);
218 SAVE(GAFR1_L); SAVE(GAFR1_U);
219 SAVE(GAFR2_L); SAVE(GAFR2_U);
220 SAVE(GAFR3_L); SAVE(GAFR3_U);
221
222 SAVE(MDREFR);
223 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
224 SAVE(PFER); SAVE(PKWR);
225
226 SAVE(CKEN);
227 SAVE(PSTR);
202 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
203
204 SAVE(GAFR0_L); SAVE(GAFR0_U);
205 SAVE(GAFR1_L); SAVE(GAFR1_U);
206 SAVE(GAFR2_L); SAVE(GAFR2_U);
207 SAVE(GAFR3_L); SAVE(GAFR3_U);
208
209 SAVE(MDREFR);
210 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
211 SAVE(PFER); SAVE(PKWR);
212
213 SAVE(CKEN);
214 SAVE(PSTR);
228
229 /* Clear GPIO transition detect bits */
230 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
231}
232
233void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
234{
235 /* ensure not to come back here if it wasn't intended */
236 PSPR = 0;
237
238 /* restore registers */
215}
216
217void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
218{
219 /* ensure not to come back here if it wasn't intended */
220 PSPR = 0;
221
222 /* restore registers */
239 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
240 RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
241 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
242 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
243 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
244 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
245 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
223 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
224 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
225 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
226 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
246 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
247 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
248 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
249
250 RESTORE(MDREFR);
251 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
252 RESTORE(PFER); RESTORE(PKWR);
253
254 PSSR = PSSR_RDH | PSSR_PH;
255

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407
408static struct sys_device pxa27x_sysdev[] = {
409 {
410 .id = 0,
411 .cls = &pxa_irq_sysclass,
412 }, {
413 .id = 1,
414 .cls = &pxa_irq_sysclass,
227 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
228
229 RESTORE(MDREFR);
230 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
231 RESTORE(PFER); RESTORE(PKWR);
232
233 PSSR = PSSR_RDH | PSSR_PH;
234

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386
387static struct sys_device pxa27x_sysdev[] = {
388 {
389 .id = 0,
390 .cls = &pxa_irq_sysclass,
391 }, {
392 .id = 1,
393 .cls = &pxa_irq_sysclass,
394 }, {
395 .cls = &pxa_gpio_sysclass,
415 },
416};
417
418static int __init pxa27x_init(void)
419{
420 int i, ret = 0;
421
422 if (cpu_is_pxa27x()) {

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397};
398
399static int __init pxa27x_init(void)
400{
401 int i, ret = 0;
402
403 if (cpu_is_pxa27x()) {

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