pxa25x.c (da1a3dc0ebb4f9209a1939eaa6b18901e0cd7bc0) pxa25x.c (5a3d96519040f9736b9f8089e2a1e33a81a6eafe)
1/*
2 * linux/arch/arm/mach-pxa/pxa25x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA21x/25x/26x variants.

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31#include <mach/reset.h>
32#include <mach/pm.h>
33#include <mach/dma.h>
34
35#include "generic.h"
36#include "devices.h"
37#include "clock.h"
38
1/*
2 * linux/arch/arm/mach-pxa/pxa25x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA21x/25x/26x variants.

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31#include <mach/reset.h>
32#include <mach/pm.h>
33#include <mach/dma.h>
34
35#include "generic.h"
36#include "devices.h"
37#include "clock.h"
38
39int cpu_is_pxa26x(void)
40{
41 return cpu_is_pxa250() && ((BOOT_DEF & 0x8) == 0);
42}
43EXPORT_SYMBOL_GPL(cpu_is_pxa26x);
44
45/*
46 * Various clock factors driven by the CCCR register.
47 */
48
49/* Crystal Frequency to Memory Frequency Multiplier (L) */
50static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
51
52/* Memory Frequency to Run Mode Frequency Multiplier (M) */

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204#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
205#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
206
207/*
208 * List of global PXA peripheral registers to preserve.
209 * More ones like CP and general purpose register values are preserved
210 * with the stack pointer in sleep.S.
211 */
39/*
40 * Various clock factors driven by the CCCR register.
41 */
42
43/* Crystal Frequency to Memory Frequency Multiplier (L) */
44static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
45
46/* Memory Frequency to Run Mode Frequency Multiplier (M) */

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198#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
199#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
200
201/*
202 * List of global PXA peripheral registers to preserve.
203 * More ones like CP and general purpose register values are preserved
204 * with the stack pointer in sleep.S.
205 */
212enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
213
214 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
215 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
216 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
217
206enum {
218 SLEEP_SAVE_PSTR,
207 SLEEP_SAVE_PSTR,
219
220 SLEEP_SAVE_CKEN,
208 SLEEP_SAVE_CKEN,
221
222 SLEEP_SAVE_COUNT
223};
224
225
226static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
227{
209 SLEEP_SAVE_COUNT
210};
211
212
213static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
214{
228 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
229
230 SAVE(GAFR0_L); SAVE(GAFR0_U);
231 SAVE(GAFR1_L); SAVE(GAFR1_U);
232 SAVE(GAFR2_L); SAVE(GAFR2_U);
233
234 SAVE(CKEN);
235 SAVE(PSTR);
215 SAVE(CKEN);
216 SAVE(PSTR);
236
237 /* Clear GPIO transition detect bits */
238 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
239}
240
241static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
242{
217}
218
219static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
220{
243 /* restore registers */
244 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
245 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
246 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
247 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
221 /* ensure not to come back here if it wasn't intended */
222 PSPR = 0;
248
223
249 PSSR = PSSR_RDH | PSSR_PH;
250
251 RESTORE(CKEN);
252 RESTORE(PSTR);
253}
254
255static void pxa25x_cpu_pm_enter(suspend_state_t state)
256{
257 /* Clear reset status */
258 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
259
260 switch (state) {
261 case PM_SUSPEND_MEM:
224 RESTORE(CKEN);
225 RESTORE(PSTR);
226}
227
228static void pxa25x_cpu_pm_enter(suspend_state_t state)
229{
230 /* Clear reset status */
231 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
232
233 switch (state) {
234 case PM_SUSPEND_MEM:
235 /* set resume return address */
236 PSPR = virt_to_phys(pxa_cpu_resume);
262 pxa25x_cpu_suspend(PWRMODE_SLEEP);
263 break;
264 }
265}
266
237 pxa25x_cpu_suspend(PWRMODE_SLEEP);
238 break;
239 }
240}
241
267static int pxa25x_cpu_pm_prepare(void)
268{
269 /* set resume return address */
270 PSPR = virt_to_phys(pxa_cpu_resume);
271 return 0;
272}
273
274static void pxa25x_cpu_pm_finish(void)
275{
276 /* ensure not to come back here if it wasn't intended */
277 PSPR = 0;
278}
279
280static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
281 .save_count = SLEEP_SAVE_COUNT,
282 .valid = suspend_valid_only_mem,
283 .save = pxa25x_cpu_pm_save,
284 .restore = pxa25x_cpu_pm_restore,
285 .enter = pxa25x_cpu_pm_enter,
242static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
243 .save_count = SLEEP_SAVE_COUNT,
244 .valid = suspend_valid_only_mem,
245 .save = pxa25x_cpu_pm_save,
246 .restore = pxa25x_cpu_pm_restore,
247 .enter = pxa25x_cpu_pm_enter,
286 .prepare = pxa25x_cpu_pm_prepare,
287 .finish = pxa25x_cpu_pm_finish,
288};
289
290static void __init pxa25x_init_pm(void)
291{
292 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
293}
294#else
295static inline void pxa25x_init_pm(void) {}

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341 &pxa25x_device_pwm0,
342 &pxa25x_device_pwm1,
343};
344
345static struct sys_device pxa25x_sysdev[] = {
346 {
347 .cls = &pxa_irq_sysclass,
348 }, {
248};
249
250static void __init pxa25x_init_pm(void)
251{
252 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
253}
254#else
255static inline void pxa25x_init_pm(void) {}

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301 &pxa25x_device_pwm0,
302 &pxa25x_device_pwm1,
303};
304
305static struct sys_device pxa25x_sysdev[] = {
306 {
307 .cls = &pxa_irq_sysclass,
308 }, {
309 .cls = &pxa2xx_mfp_sysclass,
310 }, {
349 .cls = &pxa_gpio_sysclass,
350 },
351};
352
353static int __init pxa25x_init(void)
354{
355 int i, ret = 0;
356
311 .cls = &pxa_gpio_sysclass,
312 },
313};
314
315static int __init pxa25x_init(void)
316{
317 int i, ret = 0;
318
357 if (cpu_is_pxa25x()) {
319 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
320 if (cpu_is_pxa255())
321 clks_register(&pxa25x_hwuart_clk, 1);
358
322
323 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
324
359 reset_status = RCSR;
360
361 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
362
363 if ((ret = pxa_init_dma(16)))
364 return ret;
365
366 pxa25x_init_pm();

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372 }
373
374 ret = platform_add_devices(pxa25x_devices,
375 ARRAY_SIZE(pxa25x_devices));
376 if (ret)
377 return ret;
378 }
379
325 reset_status = RCSR;
326
327 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
328
329 if ((ret = pxa_init_dma(16)))
330 return ret;
331
332 pxa25x_init_pm();

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338 }
339
340 ret = platform_add_devices(pxa25x_devices,
341 ARRAY_SIZE(pxa25x_devices));
342 if (ret)
343 return ret;
344 }
345
380 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
381 if (cpu_is_pxa255() || cpu_is_pxa26x()) {
382 clks_register(&pxa25x_hwuart_clk, 1);
346 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
347 if (cpu_is_pxa255())
383 ret = platform_device_register(&pxa_device_hwuart);
348 ret = platform_device_register(&pxa_device_hwuart);
384 }
385
386 return ret;
387}
388
389postcore_initcall(pxa25x_init);
349
350 return ret;
351}
352
353postcore_initcall(pxa25x_init);