irq.c (f43dc23d5ea91fca257be02138a255f02d98e806) irq.c (a3f4c927d379cfaa597bc8ff75dc9d28f8d9200e)
1/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
4 * Generic PXA IRQ handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.

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48
49static int pxa_internal_irq_nr;
50
51static inline int cpu_has_ipr(void)
52{
53 return !cpu_is_pxa25x();
54}
55
1/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
4 * Generic PXA IRQ handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.

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48
49static int pxa_internal_irq_nr;
50
51static inline int cpu_has_ipr(void)
52{
53 return !cpu_is_pxa25x();
54}
55
56static void pxa_mask_irq(unsigned int irq)
56static void pxa_mask_irq(struct irq_data *d)
57{
57{
58 void __iomem *base = get_irq_chip_data(irq);
58 void __iomem *base = irq_data_get_irq_chip_data(d);
59 uint32_t icmr = __raw_readl(base + ICMR);
60
59 uint32_t icmr = __raw_readl(base + ICMR);
60
61 icmr &= ~(1 << IRQ_BIT(irq));
61 icmr &= ~(1 << IRQ_BIT(d->irq));
62 __raw_writel(icmr, base + ICMR);
63}
64
62 __raw_writel(icmr, base + ICMR);
63}
64
65static void pxa_unmask_irq(unsigned int irq)
65static void pxa_unmask_irq(struct irq_data *d)
66{
66{
67 void __iomem *base = get_irq_chip_data(irq);
67 void __iomem *base = irq_data_get_irq_chip_data(d);
68 uint32_t icmr = __raw_readl(base + ICMR);
69
68 uint32_t icmr = __raw_readl(base + ICMR);
69
70 icmr |= 1 << IRQ_BIT(irq);
70 icmr |= 1 << IRQ_BIT(d->irq);
71 __raw_writel(icmr, base + ICMR);
72}
73
74static struct irq_chip pxa_internal_irq_chip = {
75 .name = "SC",
71 __raw_writel(icmr, base + ICMR);
72}
73
74static struct irq_chip pxa_internal_irq_chip = {
75 .name = "SC",
76 .ack = pxa_mask_irq,
77 .mask = pxa_mask_irq,
78 .unmask = pxa_unmask_irq,
76 .irq_ack = pxa_mask_irq,
77 .irq_mask = pxa_mask_irq,
78 .irq_unmask = pxa_unmask_irq,
79};
80
81/*
82 * GPIO IRQs for GPIO 0 and 1
83 */
79};
80
81/*
82 * GPIO IRQs for GPIO 0 and 1
83 */
84static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type)
84static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
85{
85{
86 int gpio = irq - IRQ_GPIO0;
86 int gpio = d->irq - IRQ_GPIO0;
87
88 if (__gpio_is_occupied(gpio)) {
89 pr_err("%s failed: GPIO is configured\n", __func__);
90 return -EINVAL;
91 }
92
93 if (type & IRQ_TYPE_EDGE_RISING)
94 GRER0 |= GPIO_bit(gpio);
95 else
96 GRER0 &= ~GPIO_bit(gpio);
97
98 if (type & IRQ_TYPE_EDGE_FALLING)
99 GFER0 |= GPIO_bit(gpio);
100 else
101 GFER0 &= ~GPIO_bit(gpio);
102
103 return 0;
104}
105
87
88 if (__gpio_is_occupied(gpio)) {
89 pr_err("%s failed: GPIO is configured\n", __func__);
90 return -EINVAL;
91 }
92
93 if (type & IRQ_TYPE_EDGE_RISING)
94 GRER0 |= GPIO_bit(gpio);
95 else
96 GRER0 &= ~GPIO_bit(gpio);
97
98 if (type & IRQ_TYPE_EDGE_FALLING)
99 GFER0 |= GPIO_bit(gpio);
100 else
101 GFER0 &= ~GPIO_bit(gpio);
102
103 return 0;
104}
105
106static void pxa_ack_low_gpio(unsigned int irq)
106static void pxa_ack_low_gpio(struct irq_data *d)
107{
107{
108 GEDR0 = (1 << (irq - IRQ_GPIO0));
108 GEDR0 = (1 << (d->irq - IRQ_GPIO0));
109}
110
109}
110
111static void pxa_mask_low_gpio(unsigned int irq)
111static void pxa_mask_low_gpio(struct irq_data *d)
112{
112{
113 struct irq_desc *desc = irq_to_desc(irq);
113 struct irq_desc *desc = irq_to_desc(d->irq);
114
114
115 desc->chip->mask(irq);
115 desc->irq_data.chip->irq_mask(d);
116}
117
116}
117
118static void pxa_unmask_low_gpio(unsigned int irq)
118static void pxa_unmask_low_gpio(struct irq_data *d)
119{
119{
120 struct irq_desc *desc = irq_to_desc(irq);
120 struct irq_desc *desc = irq_to_desc(d->irq);
121
121
122 desc->chip->unmask(irq);
122 desc->irq_data.chip->irq_unmask(d);
123}
124
125static struct irq_chip pxa_low_gpio_chip = {
126 .name = "GPIO-l",
123}
124
125static struct irq_chip pxa_low_gpio_chip = {
126 .name = "GPIO-l",
127 .ack = pxa_ack_low_gpio,
128 .mask = pxa_mask_low_gpio,
129 .unmask = pxa_unmask_low_gpio,
130 .set_type = pxa_set_low_gpio_type,
127 .irq_ack = pxa_ack_low_gpio,
128 .irq_mask = pxa_mask_low_gpio,
129 .irq_unmask = pxa_unmask_low_gpio,
130 .irq_set_type = pxa_set_low_gpio_type,
131};
132
133static void __init pxa_init_low_gpio_irq(set_wake_t fn)
134{
135 int irq;
136
137 /* clear edge detection on GPIO 0 and 1 */
138 GFER0 &= ~0x3;
139 GRER0 &= ~0x3;
140 GEDR0 = 0x3;
141
142 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
143 set_irq_chip(irq, &pxa_low_gpio_chip);
144 set_irq_handler(irq, handle_edge_irq);
145 set_irq_flags(irq, IRQF_VALID);
146 }
147
131};
132
133static void __init pxa_init_low_gpio_irq(set_wake_t fn)
134{
135 int irq;
136
137 /* clear edge detection on GPIO 0 and 1 */
138 GFER0 &= ~0x3;
139 GRER0 &= ~0x3;
140 GEDR0 = 0x3;
141
142 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
143 set_irq_chip(irq, &pxa_low_gpio_chip);
144 set_irq_handler(irq, handle_edge_irq);
145 set_irq_flags(irq, IRQF_VALID);
146 }
147
148 pxa_low_gpio_chip.set_wake = fn;
148 pxa_low_gpio_chip.irq_set_wake = fn;
149}
150
151static inline void __iomem *irq_base(int i)
152{
153 static unsigned long phys_base[] = {
154 0x40d00000,
155 0x40d0009c,
156 0x40d00130,

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183 set_irq_handler(irq, handle_level_irq);
184 set_irq_flags(irq, IRQF_VALID);
185 }
186 }
187
188 /* only unmasked interrupts kick us out of idle */
189 __raw_writel(1, irq_base(0) + ICCR);
190
149}
150
151static inline void __iomem *irq_base(int i)
152{
153 static unsigned long phys_base[] = {
154 0x40d00000,
155 0x40d0009c,
156 0x40d00130,

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183 set_irq_handler(irq, handle_level_irq);
184 set_irq_flags(irq, IRQF_VALID);
185 }
186 }
187
188 /* only unmasked interrupts kick us out of idle */
189 __raw_writel(1, irq_base(0) + ICCR);
190
191 pxa_internal_irq_chip.set_wake = fn;
191 pxa_internal_irq_chip.irq_set_wake = fn;
192 pxa_init_low_gpio_irq(fn);
193}
194
195#ifdef CONFIG_PM
196static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
197static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
198
199static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)

--- 53 unchanged lines hidden --- 		192 pxa_init_low_gpio_irq(fn);
193}
194
195#ifdef CONFIG_PM
196static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
197static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
198
199static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)

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