irq.c (30f0b40844e5add7ad879e2f5939ff498f72f3e6) irq.c (c95530c7798b760901c5d6212e528b03e323b8ac)
1/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.

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33 ICMR &= ~(1 << irq);
34}
35
36static void pxa_unmask_low_irq(unsigned int irq)
37{
38 ICMR |= (1 << irq);
39}
40
1/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
4 * Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.

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33 ICMR &= ~(1 << irq);
34}
35
36static void pxa_unmask_low_irq(unsigned int irq)
37{
38 ICMR |= (1 << irq);
39}
40
41static int pxa_set_wake(unsigned int irq, unsigned int on)
42{
43 u32 mask;
44
45 switch (irq) {
46 case IRQ_RTCAlrm:
47 mask = PWER_RTC;
48 break;
49#ifdef CONFIG_PXA27x
50 /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
51#endif
52 default:
53 return -EINVAL;
54 }
55 if (on)
56 PWER |= mask;
57 else
58 PWER &= ~mask;
59 return 0;
60}
61
62static struct irq_chip pxa_internal_chip_low = {
63 .name = "SC",
64 .ack = pxa_mask_low_irq,
65 .mask = pxa_mask_low_irq,
66 .unmask = pxa_unmask_low_irq,
41static struct irq_chip pxa_internal_chip_low = {
42 .name = "SC",
43 .ack = pxa_mask_low_irq,
44 .mask = pxa_mask_low_irq,
45 .unmask = pxa_unmask_low_irq,
67 .set_wake = pxa_set_wake,
68};
69
70void __init pxa_init_irq_low(void)
71{
72 int irq;
73
74 /* disable all IRQs */
75 ICMR = 0;

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120 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
121 set_irq_chip(irq, &pxa_internal_chip_high);
122 set_irq_handler(irq, handle_level_irq);
123 set_irq_flags(irq, IRQF_VALID);
124 }
125}
126#endif
127
46};
47
48void __init pxa_init_irq_low(void)
49{
50 int irq;
51
52 /* disable all IRQs */
53 ICMR = 0;

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98 for (irq = PXA_IRQ(32); irq < PXA_IRQ(64); irq++) {
99 set_irq_chip(irq, &pxa_internal_chip_high);
100 set_irq_handler(irq, handle_level_irq);
101 set_irq_flags(irq, IRQF_VALID);
102 }
103}
104#endif
105
128/* Note that if an input/irq line ever gets changed to an output during
129 * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
130 */
131#ifdef CONFIG_PXA27x
132
133/* PXA27x: Various gpios can issue wakeup events. This logic only
134 * handles the simple cases, not the WEMUX2 and WEMUX3 options
135 */
136#define PXA27x_GPIO_NOWAKE_MASK \
137 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
138#define WAKEMASK(gpio) \
139 (((gpio) <= 15) \
140 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
141 : ((gpio == 35) ? (1 << 24) : 0))
142#else
143
144/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */
145#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
146#endif
147
148/*
149 * PXA GPIO edge detection for IRQs:
150 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
151 * Use this instead of directly setting GRER/GFER.
152 */
153
154static long GPIO_IRQ_rising_edge[4];
155static long GPIO_IRQ_falling_edge[4];
156static long GPIO_IRQ_mask[4];
157
158static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
159{
160 int gpio, idx;
106/*
107 * PXA GPIO edge detection for IRQs:
108 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
109 * Use this instead of directly setting GRER/GFER.
110 */
111
112static long GPIO_IRQ_rising_edge[4];
113static long GPIO_IRQ_falling_edge[4];
114static long GPIO_IRQ_mask[4];
115
116static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
117{
118 int gpio, idx;
161 u32 mask;
162
163 gpio = IRQ_TO_GPIO(irq);
164 idx = gpio >> 5;
119
120 gpio = IRQ_TO_GPIO(irq);
121 idx = gpio >> 5;
165 mask = WAKEMASK(gpio);
166
167 if (type == IRQT_PROBE) {
168 /* Don't mess with enabled GPIOs using preconfigured edges or
169 GPIOs set to alternate function or to output during probe */
170 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
171 GPIO_bit(gpio))
172 return 0;
173 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
174 return 0;
175 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
176 }
177
178 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
179
180 pxa_gpio_mode(gpio | GPIO_IN);
181
182 if (type & __IRQT_RISEDGE) {
183 /* printk("rising "); */
184 __set_bit (gpio, GPIO_IRQ_rising_edge);
122
123 if (type == IRQT_PROBE) {
124 /* Don't mess with enabled GPIOs using preconfigured edges or
125 GPIOs set to alternate function or to output during probe */
126 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
127 GPIO_bit(gpio))
128 return 0;
129 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
130 return 0;
131 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
132 }
133
134 /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
135
136 pxa_gpio_mode(gpio | GPIO_IN);
137
138 if (type & __IRQT_RISEDGE) {
139 /* printk("rising "); */
140 __set_bit (gpio, GPIO_IRQ_rising_edge);
185 PRER |= mask;
186 } else {
187 __clear_bit (gpio, GPIO_IRQ_rising_edge);
141 } else {
142 __clear_bit (gpio, GPIO_IRQ_rising_edge);
188 PRER &= ~mask;
189 }
190
191 if (type & __IRQT_FALEDGE) {
192 /* printk("falling "); */
193 __set_bit (gpio, GPIO_IRQ_falling_edge);
143 }
144
145 if (type & __IRQT_FALEDGE) {
146 /* printk("falling "); */
147 __set_bit (gpio, GPIO_IRQ_falling_edge);
194 PFER |= mask;
195 } else {
196 __clear_bit (gpio, GPIO_IRQ_falling_edge);
148 } else {
149 __clear_bit (gpio, GPIO_IRQ_falling_edge);
197 PFER &= ~mask;
198 }
199
200 /* printk("edges\n"); */
201
202 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
203 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
204 return 0;
205}
206
207/*
208 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
209 */
210
211static void pxa_ack_low_gpio(unsigned int irq)
212{
213 GEDR0 = (1 << (irq - IRQ_GPIO0));
214}
215
150 }
151
152 /* printk("edges\n"); */
153
154 GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
155 GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
156 return 0;
157}
158
159/*
160 * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1.
161 */
162
163static void pxa_ack_low_gpio(unsigned int irq)
164{
165 GEDR0 = (1 << (irq - IRQ_GPIO0));
166}
167
216static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
217{
218 int gpio = IRQ_TO_GPIO(irq);
219 u32 mask = WAKEMASK(gpio);
220
221 if (!mask)
222 return -EINVAL;
223
224 if (on)
225 PWER |= mask;
226 else
227 PWER &= ~mask;
228 return 0;
229}
230
231
232static struct irq_chip pxa_low_gpio_chip = {
233 .name = "GPIO-l",
234 .ack = pxa_ack_low_gpio,
235 .mask = pxa_mask_low_irq,
236 .unmask = pxa_unmask_low_irq,
237 .set_type = pxa_gpio_irq_type,
168static struct irq_chip pxa_low_gpio_chip = {
169 .name = "GPIO-l",
170 .ack = pxa_ack_low_gpio,
171 .mask = pxa_mask_low_irq,
172 .unmask = pxa_unmask_low_irq,
173 .set_type = pxa_gpio_irq_type,
238 .set_wake = pxa_set_gpio_wake,
239};
240
241/*
242 * Demux handler for GPIO>=2 edge detect interrupts
243 */
244
245static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
246{

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337}
338
339static struct irq_chip pxa_muxed_gpio_chip = {
340 .name = "GPIO",
341 .ack = pxa_ack_muxed_gpio,
342 .mask = pxa_mask_muxed_gpio,
343 .unmask = pxa_unmask_muxed_gpio,
344 .set_type = pxa_gpio_irq_type,
174};
175
176/*
177 * Demux handler for GPIO>=2 edge detect interrupts
178 */
179
180static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
181{

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272}
273
274static struct irq_chip pxa_muxed_gpio_chip = {
275 .name = "GPIO",
276 .ack = pxa_ack_muxed_gpio,
277 .mask = pxa_mask_muxed_gpio,
278 .unmask = pxa_unmask_muxed_gpio,
279 .set_type = pxa_gpio_irq_type,
345 .set_wake = pxa_set_gpio_wake,
346};
347
348void __init pxa_init_irq_gpio(int gpio_nr)
349{
350 int irq, i;
351
352 pxa_last_gpio = gpio_nr - 1;
353

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372 set_irq_handler(irq, handle_edge_irq);
373 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
374 }
375
376 /* Install handler for GPIO>=2 edge detect interrupts */
377 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
378 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
379}
280};
281
282void __init pxa_init_irq_gpio(int gpio_nr)
283{
284 int irq, i;
285
286 pxa_last_gpio = gpio_nr - 1;
287

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306 set_irq_handler(irq, handle_edge_irq);
307 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
308 }
309
310 /* Install handler for GPIO>=2 edge detect interrupts */
311 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
312 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
313}
314
315void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
316{
317 pxa_internal_chip_low.set_wake = set_wake;
318#ifdef CONFIG_PXA27x
319 pxa_internal_chip_high.set_wake = set_wake;
320#endif
321 pxa_low_gpio_chip.set_wake = set_wake;
322 pxa_muxed_gpio_chip.set_wake = set_wake;
323}