pci.c (27eb2c4b3d3e13f376a359e293c212a2e9407af5) pci.c (4ca2c04085a1caa903e92a5fc0da25362150aac2)
1/*
2 * arch/arm/mach-orion5x/pci.c
3 *
4 * PCI and PCIe functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public

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152 /*
153 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 * read transaction workaround.
155 */
156 dev = orion_pcie_dev_id(PCIE_BASE);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n");
1/*
2 * arch/arm/mach-orion5x/pci.c
3 *
4 * PCI and PCIe functions for Marvell Orion System On Chip
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public

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152 /*
153 * Check whether to apply Orion-1/Orion-NAS PCIe config
154 * read transaction workaround.
155 */
156 dev = orion_pcie_dev_id(PCIE_BASE);
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n");
160 mvebu_mbus_add_window_remap_flags("pcie0.0",
161 ORION5X_PCIE_WA_PHYS_BASE,
162 ORION5X_PCIE_WA_SIZE,
163 MVEBU_MBUS_NO_REMAP,
164 MVEBU_MBUS_PCI_WA);
160 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
161 ORION_MBUS_PCIE_WA_ATTR,
162 ORION5X_PCIE_WA_PHYS_BASE,
163 ORION5X_PCIE_WA_SIZE);
165 pcie_ops.read = pcie_rd_conf_wa;
166 }
167
168 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
169
170 /*
171 * Request resources.
172 */

--- 416 unchanged lines hidden --- 		164 pcie_ops.read = pcie_rd_conf_wa;
165 }
166
167 pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
168
169 /*
170 * Request resources.
171 */

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