vc.c (08d1c9a3e2dc7a285db7c689c42963d0f5271c1f) vc.c (24d3194a2c9bc4d2315117915d4d22c395c07fd5)
1/*
2 * OMAP Voltage Controller (VC) interface
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

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14#include <plat/cpu.h>
15
16#include "voltage.h"
17#include "vc.h"
18#include "prm-regbits-34xx.h"
19#include "prm-regbits-44xx.h"
20#include "prm44xx.h"
21
1/*
2 * OMAP Voltage Controller (VC) interface
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

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14#include <plat/cpu.h>
15
16#include "voltage.h"
17#include "vc.h"
18#include "prm-regbits-34xx.h"
19#include "prm-regbits-44xx.h"
20#include "prm44xx.h"
21
22/*
23 * Channel configuration bits, common for OMAP3 & 4
24 * OMAP3 register: PRM_VC_CH_CONF
25 * OMAP4 register: PRM_VC_CFG_CHANNEL
26 */
27#define CFG_CHANNEL_SA BIT(0)
28#define CFG_CHANNEL_RAV BIT(1)
29#define CFG_CHANNEL_RAC BIT(2)
30#define CFG_CHANNEL_RACEN BIT(3)
31#define CFG_CHANNEL_CMD BIT(4)
32#define CFG_CHANNEL_MASK 0x3f
33
34/**
35 * omap_vc_config_channel - configure VC channel to PMIC mappings
36 * @voltdm: pointer to voltagdomain defining the desired VC channel
37 *
38 * Configures the VC channel to PMIC mappings for the following
39 * PMIC settings
40 * - i2c slave address (SA)
41 * - voltage configuration address (RAV)
42 * - command configuration address (RAC) and enable bit (RACEN)
43 * - command values for ON, ONLP, RET and OFF (CMD)
44 *
45 * This function currently only allows flexible configuration of the
46 * non-default channel. Starting with OMAP4, there are more than 2
47 * channels, with one defined as the default (on OMAP4, it's MPU.)
48 * Only the non-default channel can be configured.
49 */
50static int omap_vc_config_channel(struct voltagedomain *voltdm)
51{
52 struct omap_vc_channel *vc = voltdm->vc;
53
54 /*
55 * For default channel, the only configurable bit is RACEN.
56 * All others must stay at zero (see function comment above.)
57 */
58 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
59 vc->cfg_channel &= CFG_CHANNEL_RACEN;
60
61 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
62 vc->cfg_channel << vc->cfg_channel_sa_shift,
63 vc->common->cfg_channel_reg);
64
65 return 0;
66}
67
22/* Voltage scale and accessory APIs */
23int omap_vc_pre_scale(struct voltagedomain *voltdm,
24 unsigned long target_volt,
25 u8 *target_vsel, u8 *current_vsel)
26{
27 struct omap_vc_channel *vc = voltdm->vc;
28 struct omap_vdd_info *vdd = voltdm->vdd;
29 struct omap_volt_data *volt_data;

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161
162 if (is_initialized)
163 return;
164
165 /*
166 * Generic VC parameters init
167 * XXX This data should be abstracted out
168 */
68/* Voltage scale and accessory APIs */
69int omap_vc_pre_scale(struct voltagedomain *voltdm,
70 unsigned long target_volt,
71 u8 *target_vsel, u8 *current_vsel)
72{
73 struct omap_vc_channel *vc = voltdm->vc;
74 struct omap_vdd_info *vdd = voltdm->vdd;
75 struct omap_volt_data *volt_data;

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207
208 if (is_initialized)
209 return;
210
211 /*
212 * Generic VC parameters init
213 * XXX This data should be abstracted out
214 */
169 voltdm->write(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK,
170 OMAP3_PRM_VC_CH_CONF_OFFSET);
171 voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
172 OMAP3_PRM_VC_I2C_CFG_OFFSET);
173
174 omap3_vfsm_init(voltdm);
175
176 is_initialized = true;
177}
178
179
180/* OMAP4 specific voltage init functions */
181static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
182{
183 static bool is_initialized;
184 u32 vc_val;
185
186 if (is_initialized)
187 return;
188
215 voltdm->write(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK,
216 OMAP3_PRM_VC_I2C_CFG_OFFSET);
217
218 omap3_vfsm_init(voltdm);
219
220 is_initialized = true;
221}
222
223
224/* OMAP4 specific voltage init functions */
225static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
226{
227 static bool is_initialized;
228 u32 vc_val;
229
230 if (is_initialized)
231 return;
232
189 /*
190 * Generic VC parameters init
191 * XXX This data should be abstracted out
192 */
193 vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
194 OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
195 OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
196 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
197
198 /* XXX These are magic numbers and do not belong! */
199 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
200 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
201
202 is_initialized = true;
203}
204
205void __init omap_vc_init_channel(struct voltagedomain *voltdm)

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217 }
218
219 if (!voltdm->read || !voltdm->write) {
220 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
221 __func__, voltdm->name);
222 return;
223 }
224
233 /* XXX These are magic numbers and do not belong! */
234 vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
235 voltdm->write(vc_val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
236
237 is_initialized = true;
238}
239
240void __init omap_vc_init_channel(struct voltagedomain *voltdm)

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252 }
253
254 if (!voltdm->read || !voltdm->write) {
255 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
256 __func__, voltdm->name);
257 return;
258 }
259
260 vc->cfg_channel = 0;
261
225 /* get PMIC/board specific settings */
226 vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
227 vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
228 vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
229 vc->setup_time = vdd->pmic_info->volt_setup_time;
230
231 /* Configure the i2c slave address for this VC */
232 voltdm->rmw(vc->smps_sa_mask,
233 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
234 vc->common->smps_sa_reg);
262 /* get PMIC/board specific settings */
263 vc->i2c_slave_addr = vdd->pmic_info->i2c_slave_addr;
264 vc->volt_reg_addr = vdd->pmic_info->volt_reg_addr;
265 vc->cmd_reg_addr = vdd->pmic_info->cmd_reg_addr;
266 vc->setup_time = vdd->pmic_info->volt_setup_time;
267
268 /* Configure the i2c slave address for this VC */
269 voltdm->rmw(vc->smps_sa_mask,
270 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
271 vc->common->smps_sa_reg);
272 vc->cfg_channel |= CFG_CHANNEL_SA;
235
236 /*
237 * Configure the PMIC register addresses.
238 */
239 voltdm->rmw(vc->smps_volra_mask,
240 vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
241 vc->common->smps_volra_reg);
273
274 /*
275 * Configure the PMIC register addresses.
276 */
277 voltdm->rmw(vc->smps_volra_mask,
278 vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
279 vc->common->smps_volra_reg);
242 if (vc->cmd_reg_addr)
280 vc->cfg_channel |= CFG_CHANNEL_RAV;
281
282 if (vc->cmd_reg_addr) {
243 voltdm->rmw(vc->smps_cmdra_mask,
244 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
245 vc->common->smps_cmdra_reg);
283 voltdm->rmw(vc->smps_cmdra_mask,
284 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
285 vc->common->smps_cmdra_reg);
286 vc->cfg_channel |= CFG_CHANNEL_RAC | CFG_CHANNEL_RACEN;
287 }
246
247 /* Set up the on, inactive, retention and off voltage */
248 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
249 onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
250 ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
251 off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
252 val = ((on_vsel << vc->common->cmd_on_shift) |
253 (onlp_vsel << vc->common->cmd_onlp_shift) |
254 (ret_vsel << vc->common->cmd_ret_shift) |
255 (off_vsel << vc->common->cmd_off_shift));
256 voltdm->write(val, vc->cmdval_reg);
288
289 /* Set up the on, inactive, retention and off voltage */
290 on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
291 onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
292 ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
293 off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
294 val = ((on_vsel << vc->common->cmd_on_shift) |
295 (onlp_vsel << vc->common->cmd_onlp_shift) |
296 (ret_vsel << vc->common->cmd_ret_shift) |
297 (off_vsel << vc->common->cmd_off_shift));
298 voltdm->write(val, vc->cmdval_reg);
299 vc->cfg_channel |= CFG_CHANNEL_CMD;
257
300
301 /* Channel configuration */
302 omap_vc_config_channel(voltdm);
303
258 /* Configure the setup times */
259 voltdm->rmw(voltdm->vfsm->voltsetup_mask,
260 vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
261 voltdm->vfsm->voltsetup_reg);
262
263 if (cpu_is_omap34xx())
264 omap3_vc_init_channel(voltdm);
265 else if (cpu_is_omap44xx())
266 omap4_vc_init_channel(voltdm);
267}
268
304 /* Configure the setup times */
305 voltdm->rmw(voltdm->vfsm->voltsetup_mask,
306 vc->setup_time << __ffs(voltdm->vfsm->voltsetup_mask),
307 voltdm->vfsm->voltsetup_reg);
308
309 if (cpu_is_omap34xx())
310 omap3_vc_init_channel(voltdm);
311 else if (cpu_is_omap44xx())
312 omap4_vc_init_channel(voltdm);
313}
314