| sram242x.S (373a67021d00a8b8c86bfa19f8914377de05b4bd) | sram242x.S (c2d43e39c7c303db53facd0bea44b66f263e3f35) |
|---|---|
| 1/* | 1/* |
| 2 * linux/arch/arm/mach-omap2/sram-fn.S | 2 * linux/arch/arm/mach-omap2/sram242x.S |
| 3 * 4 * Omap2 specific functions that need to be run in internal SRAM 5 * 6 * (C) Copyright 2004 7 * Texas Instruments, <www.ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or --- 11 unchanged lines hidden (view full) --- 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25#include <linux/linkage.h> 26#include <asm/assembler.h> 27#include <asm/arch/io.h> 28#include <asm/hardware.h> 29 | 3 * 4 * Omap2 specific functions that need to be run in internal SRAM 5 * 6 * (C) Copyright 2004 7 * Texas Instruments, <www.ti.com> 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or --- 11 unchanged lines hidden (view full) --- 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25#include <linux/linkage.h> 26#include <asm/assembler.h> 27#include <asm/arch/io.h> 28#include <asm/hardware.h> 29 |
| 30#include "sdrc.h" | |
| 31#include "prm.h" 32#include "cm.h" | 30#include "prm.h" 31#include "cm.h" |
| 32#include "sdrc.h" |
|
| 33 | 33 |
| 34#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010) 35 | |
| 36 .text 37 | 34 .text 35 |
| 38ENTRY(sram_ddr_init) | 36ENTRY(omap242x_sram_ddr_init) |
| 39 stmfd sp!, {r0 - r12, lr} @ save registers on stack 40 41 mov r12, r2 @ capture CS1 vs CS0 42 mov r8, r3 @ capture force parameter 43 44 /* frequency shift down */ | 37 stmfd sp!, {r0 - r12, lr} @ save registers on stack 38 39 mov r12, r2 @ capture CS1 vs CS0 40 mov r8, r3 @ capture force parameter 41 42 /* frequency shift down */ |
| 45 ldr r2, cm_clksel2_pll @ get address of dpllout reg | 43 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg |
| 46 mov r3, #0x1 @ value for 1x operation 47 str r3, [r2] @ go to L1-freq operation 48 49 /* voltage shift down */ 50 mov r9, #0x1 @ set up for L1 voltage call 51 bl voltage_shift @ go drop voltage 52 53 /* dll lock mode */ | 44 mov r3, #0x1 @ value for 1x operation 45 str r3, [r2] @ go to L1-freq operation 46 47 /* voltage shift down */ 48 mov r9, #0x1 @ set up for L1 voltage call 49 bl voltage_shift @ go drop voltage 50 51 /* dll lock mode */ |
| 54 ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl | 52 ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl |
| 55 ldr r10, [r11] @ get current val 56 cmp r12, #0x1 @ cs1 base (2422 es2.05/1) 57 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB 58 mvn r9, #0x4 @ mask to get clear bit2 59 and r10, r10, r9 @ clear bit2 for lock mode. 60 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 61 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz 62 str r10, [r11] @ commit to DLLA_CTRL --- 34 unchanged lines hidden (view full) --- 97 bne i_dll_delay 98 mov pc, lr 99 100 /* 101 * shift up or down voltage, use R9 as input to tell level. 102 * wait for it to finish, use 32k sync counter, 1tick=31uS. 103 */ 104voltage_shift: | 53 ldr r10, [r11] @ get current val 54 cmp r12, #0x1 @ cs1 base (2422 es2.05/1) 55 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB 56 mvn r9, #0x4 @ mask to get clear bit2 57 and r10, r10, r9 @ clear bit2 for lock mode. 58 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 59 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz 60 str r10, [r11] @ commit to DLLA_CTRL --- 34 unchanged lines hidden (view full) --- 95 bne i_dll_delay 96 mov pc, lr 97 98 /* 99 * shift up or down voltage, use R9 as input to tell level. 100 * wait for it to finish, use 32k sync counter, 1tick=31uS. 101 */ 102voltage_shift: |
| 105 ldr r4, prcm_voltctrl @ get addr of volt ctrl. | 103 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl. |
| 106 ldr r5, [r4] @ get value. 107 ldr r6, prcm_mask_val @ get value of mask 108 and r5, r5, r6 @ apply mask to clear bits 109 orr r5, r5, r9 @ bulld value for L0/L1-volt operation. 110 str r5, [r4] @ set up for change. 111 mov r3, #0x4000 @ get val for force 112 orr r5, r5, r3 @ build value for force 113 str r5, [r4] @ Force transition to L1 114 | 104 ldr r5, [r4] @ get value. 105 ldr r6, prcm_mask_val @ get value of mask 106 and r5, r5, r6 @ apply mask to clear bits 107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation. 108 str r5, [r4] @ set up for change. 109 mov r3, #0x4000 @ get val for force 110 orr r5, r5, r3 @ build value for force 111 str r5, [r4] @ Force transition to L1 112 |
| 115 ldr r3, timer_32ksynct_cr @ get addr of counter | 113 ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter |
| 116 ldr r5, [r3] @ get value 117 add r5, r5, #0x3 @ give it at most 93uS 118volt_delay: 119 ldr r7, [r3] @ get timer value 120 cmp r5, r7 @ time up? 121 bhi volt_delay @ not yet->branch 122 mov pc, lr @ back to caller. 123 | 114 ldr r5, [r3] @ get value 115 add r5, r5, #0x3 @ give it at most 93uS 116volt_delay: 117 ldr r7, [r3] @ get timer value 118 cmp r5, r7 @ time up? 119 bhi volt_delay @ not yet->branch 120 mov pc, lr @ back to caller. 121 |
| 124/* relative load constants */ 125cm_clksel2_pll: | 122omap242x_sdi_cm_clksel2_pll: |
| 126 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) | 123 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) |
| 127sdrc_dlla_ctrl: | 124omap242x_sdi_sdrc_dlla_ctrl: |
| 128 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) | 125 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 129prcm_voltctrl: 130 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) | 126omap242x_sdi_prcm_voltctrl: 127 .word OMAP242X_PRCM_VOLTCTRL |
| 131prcm_mask_val: 132 .word 0xFFFF3FFC | 128prcm_mask_val: 129 .word 0xFFFF3FFC |
| 133timer_32ksynct_cr: 134 .word TIMER_32KSYNCT_CR_V 135ENTRY(sram_ddr_init_sz) 136 .word . - sram_ddr_init | 130omap242x_sdi_timer_32ksynct_cr: 131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) 132ENTRY(omap242x_sram_ddr_init_sz) 133 .word . - omap242x_sram_ddr_init |
| 137 138/* 139 * Reprograms memory timings. 140 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] 141 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 142 */ | 134 135/* 136 * Reprograms memory timings. 137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] 138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 139 */ |
| 143ENTRY(sram_reprogram_sdrc) | 140ENTRY(omap242x_sram_reprogram_sdrc) |
| 144 stmfd sp!, {r0 - r10, lr} @ save registers on stack 145 mov r3, #0x0 @ clear for mrc call 146 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 147 nop 148 nop | 141 stmfd sp!, {r0 - r10, lr} @ save registers on stack 142 mov r3, #0x0 @ clear for mrc call 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 144 nop 145 nop |
| 149 ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg | 146 ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg |
| 150 ldr r5, [r6] @ get value 151 mov r5, r5, lsr #8 @ isolate rfr field and drop burst 152 153 cmp r0, #0x1 @ going to half speed? 154 movne r9, #0x0 @ if up set flag up for pre up, hi volt 155 156 blne voltage_shift_c @ adjust voltage 157 158 cmp r0, #0x1 @ going to half speed (post branch link) 159 moveq r5, r5, lsr #1 @ divide by 2 if to half 160 movne r5, r5, lsl #1 @ mult by 2 if to full 161 mov r5, r5, lsl #8 @ put rfr field back into place 162 add r5, r5, #0x1 @ turn on burst of 1 | 147 ldr r5, [r6] @ get value 148 mov r5, r5, lsr #8 @ isolate rfr field and drop burst 149 150 cmp r0, #0x1 @ going to half speed? 151 movne r9, #0x0 @ if up set flag up for pre up, hi volt 152 153 blne voltage_shift_c @ adjust voltage 154 155 cmp r0, #0x1 @ going to half speed (post branch link) 156 moveq r5, r5, lsr #1 @ divide by 2 if to half 157 movne r5, r5, lsl #1 @ mult by 2 if to full 158 mov r5, r5, lsl #8 @ put rfr field back into place 159 add r5, r5, #0x1 @ turn on burst of 1 |
| 163 ldr r4, ddr_cm_clksel2_pll @ get address of out reg | 160 ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg |
| 164 ldr r3, [r4] @ get curr value 165 orr r3, r3, #0x3 166 bic r3, r3, #0x3 @ clear lower bits 167 orr r3, r3, r0 @ new state value 168 str r3, [r4] @ set new state (pll/x, x=1 or 2) 169 nop 170 nop 171 --- 4 unchanged lines hidden (view full) --- 176 str r5, [r6] @ set new RFR_1 value 177 add r6, r6, #0x30 @ get RFR_2 addr 178 str r5, [r6] @ set RFR_2 179 nop 180 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL 181 bne freq_out @ leave if SDR, no DLL function 182 183 /* With DDR, we need to take care of the DLL for the frequency change */ | 161 ldr r3, [r4] @ get curr value 162 orr r3, r3, #0x3 163 bic r3, r3, #0x3 @ clear lower bits 164 orr r3, r3, r0 @ new state value 165 str r3, [r4] @ set new state (pll/x, x=1 or 2) 166 nop 167 nop 168 --- 4 unchanged lines hidden (view full) --- 173 str r5, [r6] @ set new RFR_1 value 174 add r6, r6, #0x30 @ get RFR_2 addr 175 str r5, [r6] @ set RFR_2 176 nop 177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL 178 bne freq_out @ leave if SDR, no DLL function 179 180 /* With DDR, we need to take care of the DLL for the frequency change */ |
| 184 ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl | 181 ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl |
| 185 str r1, [r2] @ write out new SDRC_DLLA_CTRL 186 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL 187 str r1, [r2] @ commit to SDRC_DLLB_CTRL 188 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 189dll_wait: 190 subs r1, r1, #0x1 191 bne dll_wait 192freq_out: 193 ldmfd sp!, {r0 - r10, pc} @ restore regs and return 194 195 /* 196 * shift up or down voltage, use R9 as input to tell level. 197 * wait for it to finish, use 32k sync counter, 1tick=31uS. 198 */ 199voltage_shift_c: | 182 str r1, [r2] @ write out new SDRC_DLLA_CTRL 183 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL 184 str r1, [r2] @ commit to SDRC_DLLB_CTRL 185 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks 186dll_wait: 187 subs r1, r1, #0x1 188 bne dll_wait 189freq_out: 190 ldmfd sp!, {r0 - r10, pc} @ restore regs and return 191 192 /* 193 * shift up or down voltage, use R9 as input to tell level. 194 * wait for it to finish, use 32k sync counter, 1tick=31uS. 195 */ 196voltage_shift_c: |
| 200 ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl | 197 ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl |
| 201 ldr r8, [r10] @ get value 202 ldr r7, ddr_prcm_mask_val @ get value of mask 203 and r8, r8, r7 @ apply mask to clear bits 204 orr r8, r8, r9 @ bulld value for L0/L1-volt operation. 205 str r8, [r10] @ set up for change. 206 mov r7, #0x4000 @ get val for force 207 orr r8, r8, r7 @ build value for force 208 str r8, [r10] @ Force transition to L1 209 | 198 ldr r8, [r10] @ get value 199 ldr r7, ddr_prcm_mask_val @ get value of mask 200 and r8, r8, r7 @ apply mask to clear bits 201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation. 202 str r8, [r10] @ set up for change. 203 mov r7, #0x4000 @ get val for force 204 orr r8, r8, r7 @ build value for force 205 str r8, [r10] @ Force transition to L1 206 |
| 210 ldr r10, ddr_timer_32ksynct @ get addr of counter | 207 ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter |
| 211 ldr r8, [r10] @ get value 212 add r8, r8, #0x2 @ give it at most 62uS (min 31+) 213volt_delay_c: 214 ldr r7, [r10] @ get timer value 215 cmp r8, r7 @ time up? 216 bhi volt_delay_c @ not yet->branch 217 mov pc, lr @ back to caller 218 | 208 ldr r8, [r10] @ get value 209 add r8, r8, #0x2 @ give it at most 62uS (min 31+) 210volt_delay_c: 211 ldr r7, [r10] @ get timer value 212 cmp r8, r7 @ time up? 213 bhi volt_delay_c @ not yet->branch 214 mov pc, lr @ back to caller 215 |
| 219ddr_cm_clksel2_pll: | 216omap242x_srs_cm_clksel2_pll: |
| 220 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) | 217 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) |
| 221ddr_sdrc_dlla_ctrl: | 218omap242x_srs_sdrc_dlla_ctrl: |
| 222 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) | 219 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) |
| 223ddr_sdrc_rfr_ctrl: | 220omap242x_srs_sdrc_rfr_ctrl: |
| 224 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) | 221 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
| 225ddr_prcm_voltctrl: 226 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) | 222omap242x_srs_prcm_voltctrl: 223 .word OMAP242X_PRCM_VOLTCTRL |
| 227ddr_prcm_mask_val: 228 .word 0xFFFF3FFC | 224ddr_prcm_mask_val: 225 .word 0xFFFF3FFC |
| 229ddr_timer_32ksynct: 230 .word TIMER_32KSYNCT_CR_V | 226omap242x_srs_timer_32ksynct: 227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) |
| 231 | 228 |
| 232ENTRY(sram_reprogram_sdrc_sz) 233 .word . - sram_reprogram_sdrc | 229ENTRY(omap242x_sram_reprogram_sdrc_sz) 230 .word . - omap242x_sram_reprogram_sdrc |
| 234 235/* 236 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. 237 */ | 231 232/* 233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. 234 */ |
| 238ENTRY(sram_set_prcm) | 235ENTRY(omap242x_sram_set_prcm) |
| 239 stmfd sp!, {r0-r12, lr} @ regs to stack 240 adr r4, pbegin @ addr of preload start 241 adr r8, pend @ addr of preload end 242 mcrr p15, 1, r8, r4, c12 @ preload into icache 243pbegin: 244 /* move into fast relock bypass */ | 236 stmfd sp!, {r0-r12, lr} @ regs to stack 237 adr r4, pbegin @ addr of preload start 238 adr r8, pend @ addr of preload end 239 mcrr p15, 1, r8, r4, c12 @ preload into icache 240pbegin: 241 /* move into fast relock bypass */ |
| 245 ldr r8, pll_ctl @ get addr | 242 ldr r8, omap242x_ssp_pll_ctl @ get addr |
| 246 ldr r5, [r8] @ get val 247 mvn r6, #0x3 @ clear mask 248 and r5, r5, r6 @ clear field 249 orr r7, r5, #0x2 @ fast relock val 250 str r7, [r8] @ go to fast relock | 243 ldr r5, [r8] @ get val 244 mvn r6, #0x3 @ clear mask 245 and r5, r5, r6 @ clear field 246 orr r7, r5, #0x2 @ fast relock val 247 str r7, [r8] @ go to fast relock |
| 251 ldr r4, pll_stat @ addr of stat | 248 ldr r4, omap242x_ssp_pll_stat @ addr of stat |
| 252block: 253 /* wait for bypass */ 254 ldr r8, [r4] @ stat value 255 and r8, r8, #0x3 @ mask for stat 256 cmp r8, #0x1 @ there yet 257 bne block @ loop if not 258 259 /* set new dpll dividers _after_ in bypass */ | 249block: 250 /* wait for bypass */ 251 ldr r8, [r4] @ stat value 252 and r8, r8, #0x3 @ mask for stat 253 cmp r8, #0x1 @ there yet 254 bne block @ loop if not 255 256 /* set new dpll dividers _after_ in bypass */ |
| 260 ldr r4, pll_div @ get addr | 257 ldr r4, omap242x_ssp_pll_div @ get addr |
| 261 str r0, [r4] @ set dpll ctrl val 262 | 258 str r0, [r4] @ set dpll ctrl val 259 |
| 263 ldr r4, set_config @ get addr | 260 ldr r4, omap242x_ssp_set_config @ get addr |
| 264 mov r8, #1 @ valid cfg msk 265 str r8, [r4] @ make dividers take 266 267 mov r4, #100 @ dead spin a bit 268wait_a_bit: 269 subs r4, r4, #1 @ dec loop 270 bne wait_a_bit @ delay done? 271 272 /* check if staying in bypass */ 273 cmp r2, #0x1 @ stay in bypass? 274 beq pend @ jump over dpll relock 275 276 /* relock DPLL with new vals */ | 261 mov r8, #1 @ valid cfg msk 262 str r8, [r4] @ make dividers take 263 264 mov r4, #100 @ dead spin a bit 265wait_a_bit: 266 subs r4, r4, #1 @ dec loop 267 bne wait_a_bit @ delay done? 268 269 /* check if staying in bypass */ 270 cmp r2, #0x1 @ stay in bypass? 271 beq pend @ jump over dpll relock 272 273 /* relock DPLL with new vals */ |
| 277 ldr r5, pll_stat @ get addr 278 ldr r4, pll_ctl @ get addr | 274 ldr r5, omap242x_ssp_pll_stat @ get addr 275 ldr r4, omap242x_ssp_pll_ctl @ get addr |
| 279 orr r8, r7, #0x3 @ val for lock dpll 280 str r8, [r4] @ set val 281 mov r0, #1000 @ dead spin a bit 282wait_more: 283 subs r0, r0, #1 @ dec loop 284 bne wait_more @ delay done? 285wait_lock: 286 ldr r8, [r5] @ get lock val 287 and r8, r8, #3 @ isolate field 288 cmp r8, #2 @ locked? 289 bne wait_lock @ wait if not 290pend: 291 /* update memory timings & briefly lock dll */ | 276 orr r8, r7, #0x3 @ val for lock dpll 277 str r8, [r4] @ set val 278 mov r0, #1000 @ dead spin a bit 279wait_more: 280 subs r0, r0, #1 @ dec loop 281 bne wait_more @ delay done? 282wait_lock: 283 ldr r8, [r5] @ get lock val 284 and r8, r8, #3 @ isolate field 285 cmp r8, #2 @ locked? 286 bne wait_lock @ wait if not 287pend: 288 /* update memory timings & briefly lock dll */ |
| 292 ldr r4, sdrc_rfr @ get addr | 289 ldr r4, omap242x_ssp_sdrc_rfr @ get addr |
| 293 str r1, [r4] @ update refresh timing | 290 str r1, [r4] @ update refresh timing |
| 294 ldr r11, dlla_ctrl @ get addr of DLLA ctrl | 291 ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl |
| 295 ldr r10, [r11] @ get current val 296 mvn r9, #0x4 @ mask to get clear bit2 297 and r10, r10, r9 @ clear bit2 for lock mode 298 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 299 str r10, [r11] @ commit to DLLA_CTRL 300 add r11, r11, #0x8 @ move to dllb 301 str r10, [r11] @ hit DLLB also 302 303 mov r4, #0x800 @ relock time (min 0x400 L3 clocks) 304wait_dll_lock: 305 subs r4, r4, #0x1 306 bne wait_dll_lock 307 nop 308 ldmfd sp!, {r0-r12, pc} @ restore regs and return 309 | 292 ldr r10, [r11] @ get current val 293 mvn r9, #0x4 @ mask to get clear bit2 294 and r10, r10, r9 @ clear bit2 for lock mode 295 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) 296 str r10, [r11] @ commit to DLLA_CTRL 297 add r11, r11, #0x8 @ move to dllb 298 str r10, [r11] @ hit DLLB also 299 300 mov r4, #0x800 @ relock time (min 0x400 L3 clocks) 301wait_dll_lock: 302 subs r4, r4, #0x1 303 bne wait_dll_lock 304 nop 305 ldmfd sp!, {r0-r12, pc} @ restore regs and return 306 |
| 310set_config: 311 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80) 312pll_ctl: 313 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1) 314pll_stat: 315 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1) 316pll_div: 317 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL) 318sdrc_rfr: | 307omap242x_ssp_set_config: 308 .word OMAP242X_PRCM_CLKCFG_CTRL 309omap242x_ssp_pll_ctl: 310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN) 311omap242x_ssp_pll_stat: 312 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST) 313omap242x_ssp_pll_div: 314 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1) 315omap242x_ssp_sdrc_rfr: |
| 319 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) | 316 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) |
| 320dlla_ctrl: | 317omap242x_ssp_dlla_ctrl: |
| 321 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 322 | 318 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 319 |
| 323ENTRY(sram_set_prcm_sz) 324 .word . - sram_set_prcm | 320ENTRY(omap242x_sram_set_prcm_sz) 321 .word . - omap242x_sram_set_prcm |