sleep43xx.S (6b16f5d12202a23d875915349cc031c07fe1b3ec) sleep43xx.S (74655749a58405e259eaaba66bfc391fdbe1e34e)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Low level suspend code for AM43XX SoCs
4 *
5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Dave Gerlach, Vaibhav Bedia
7 */
8
9#include <generated/ti-pm-asm-offsets.h>
10#include <linux/linkage.h>
11#include <linux/ti-emif-sram.h>
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Low level suspend code for AM43XX SoCs
4 *
5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Dave Gerlach, Vaibhav Bedia
7 */
8
9#include <generated/ti-pm-asm-offsets.h>
10#include <linux/linkage.h>
11#include <linux/ti-emif-sram.h>
12
12#include <linux/platform_data/pm33xx.h>
13#include <asm/assembler.h>
14#include <asm/hardware/cache-l2x0.h>
15#include <asm/memory.h>
16
17#include "cm33xx.h"
18#include "common.h"
19#include "iomap.h"
20#include "omap-secure.h"
21#include "omap44xx.h"
22#include "prm33xx.h"
23#include "prcm43xx.h"
24
13#include <asm/assembler.h>
14#include <asm/hardware/cache-l2x0.h>
15#include <asm/memory.h>
16
17#include "cm33xx.h"
18#include "common.h"
19#include "iomap.h"
20#include "omap-secure.h"
21#include "omap44xx.h"
22#include "prm33xx.h"
23#include "prcm43xx.h"
24
25/* replicated define because linux/bitops.h cannot be included in assembly */
26#define BIT(nr) (1 << (nr))
27
25#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
26#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
27#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
28
29#define AM43XX_EMIF_POWEROFF_ENABLE 0x1
30#define AM43XX_EMIF_POWEROFF_DISABLE 0x0
31
32#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP 0x1

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46#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
47
48 .arm
49 .align 3
50
51ENTRY(am43xx_do_wfi)
52 stmfd sp!, {r4 - r11, lr} @ save registers on stack
53
28#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
29#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
30#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
31
32#define AM43XX_EMIF_POWEROFF_ENABLE 0x1
33#define AM43XX_EMIF_POWEROFF_DISABLE 0x0
34
35#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP 0x1

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49#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
50
51 .arm
52 .align 3
53
54ENTRY(am43xx_do_wfi)
55 stmfd sp!, {r4 - r11, lr} @ save registers on stack
56
57 /* Save wfi_flags arg to data space */
58 mov r4, r0
59 adr r3, am43xx_pm_ro_sram_data
60 ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
61 str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
62
54#ifdef CONFIG_CACHE_L2X0
55 /* Retrieve l2 cache virt address BEFORE we shut off EMIF */
56 ldr r1, get_l2cache_base
57 blx r1
58 mov r8, r0
59#endif
60
63#ifdef CONFIG_CACHE_L2X0
64 /* Retrieve l2 cache virt address BEFORE we shut off EMIF */
65 ldr r1, get_l2cache_base
66 blx r1
67 mov r8, r0
68#endif
69
70 /* Only flush cache is we know we are losing MPU context */
71 tst r4, #WFI_FLAG_FLUSH_CACHE
72 beq cache_skip_flush
73
61 /*
62 * Flush all data from the L1 and L2 data cache before disabling
63 * SCTLR.C bit.
64 */
65 ldr r1, kernel_flush
66 blx r1
67
68 /*

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123 mov r0, #0x0
124 str r0, [r2, #L2X0_CACHE_SYNC]
125sync:
126 ldr r0, [r2, #L2X0_CACHE_SYNC]
127 ands r0, r0, #0x1
128 bne sync
129#endif
130
74 /*
75 * Flush all data from the L1 and L2 data cache before disabling
76 * SCTLR.C bit.
77 */
78 ldr r1, kernel_flush
79 blx r1
80
81 /*

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136 mov r0, #0x0
137 str r0, [r2, #L2X0_CACHE_SYNC]
138sync:
139 ldr r0, [r2, #L2X0_CACHE_SYNC]
140 ands r0, r0, #0x1
141 bne sync
142#endif
143
144 /* Restore wfi_flags */
145 adr r3, am43xx_pm_ro_sram_data
146 ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
147 ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
148
149cache_skip_flush:
150 /* Check if we want self refresh */
151 tst r4, #WFI_FLAG_SELF_REFRESH
152 beq emif_skip_enter_sr
153
131 adr r9, am43xx_emif_sram_table
132
133 ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
134 blx r3
135
154 adr r9, am43xx_emif_sram_table
155
156 ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
157 blx r3
158
159emif_skip_enter_sr:
160 /* Only necessary if PER is losing context */
161 tst r4, #WFI_FLAG_SAVE_EMIF
162 beq emif_skip_save
163
136 ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
164 ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
137 blx r3
165 blx r3
138
166
167emif_skip_save:
168 /* Only can disable EMIF if we have entered self refresh */
169 tst r4, #WFI_FLAG_SELF_REFRESH
170 beq emif_skip_disable
171
139 /* Disable EMIF */
140 ldr r1, am43xx_virt_emif_clkctrl
141 ldr r2, [r1]
142 bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
143 str r2, [r1]
144
145wait_emif_disable:
146 ldr r2, [r1]
147 mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
148 cmp r2, r3
149 bne wait_emif_disable
150
172 /* Disable EMIF */
173 ldr r1, am43xx_virt_emif_clkctrl
174 ldr r2, [r1]
175 bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
176 str r2, [r1]
177
178wait_emif_disable:
179 ldr r2, [r1]
180 mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED
181 cmp r2, r3
182 bne wait_emif_disable
183
184emif_skip_disable:
185 tst r4, #WFI_FLAG_WAKE_M3
186 beq wkup_m3_skip
187
151 /*
152 * For the MPU WFI to be registered as an interrupt
153 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
154 * to DISABLED
155 */
156 ldr r1, am43xx_virt_mpu_clkctrl
157 ldr r2, [r1]
158 bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
159 str r2, [r1]
160
161 /*
162 * Put MPU CLKDM to SW_SLEEP
163 */
164 ldr r1, am43xx_virt_mpu_clkstctrl
165 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
166 str r2, [r1]
167
188 /*
189 * For the MPU WFI to be registered as an interrupt
190 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
191 * to DISABLED
192 */
193 ldr r1, am43xx_virt_mpu_clkctrl
194 ldr r2, [r1]
195 bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
196 str r2, [r1]
197
198 /*
199 * Put MPU CLKDM to SW_SLEEP
200 */
201 ldr r1, am43xx_virt_mpu_clkstctrl
202 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
203 str r2, [r1]
204
205wkup_m3_skip:
168 /*
169 * Execute a barrier instruction to ensure that all cache,
170 * TLB and branch predictor maintenance operations issued
171 * have completed.
172 */
173 dsb
174 dmb
175

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213 ldr r1, am43xx_virt_emif_clkctrl
214 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
215 str r2, [r1]
216wait_emif_enable:
217 ldr r3, [r1]
218 cmp r2, r3
219 bne wait_emif_enable
220
206 /*
207 * Execute a barrier instruction to ensure that all cache,
208 * TLB and branch predictor maintenance operations issued
209 * have completed.
210 */
211 dsb
212 dmb
213

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251 ldr r1, am43xx_virt_emif_clkctrl
252 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
253 str r2, [r1]
254wait_emif_enable:
255 ldr r3, [r1]
256 cmp r2, r3
257 bne wait_emif_enable
258
259 tst r4, #WFI_FLAG_FLUSH_CACHE
260 beq cache_skip_restore
261
221 /*
222 * Set SCTLR.C bit to allow data cache allocation
223 */
224 mrc p15, 0, r0, c1, c0, 0
225 orr r0, r0, #(1 << 2) @ Enable the C bit
226 mcr p15, 0, r0, c1, c0, 0
227 isb
228
262 /*
263 * Set SCTLR.C bit to allow data cache allocation
264 */
265 mrc p15, 0, r0, c1, c0, 0
266 orr r0, r0, #(1 << 2) @ Enable the C bit
267 mcr p15, 0, r0, c1, c0, 0
268 isb
269
229 ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
230 blx r1
270cache_skip_restore:
271 /* Only necessary if PER is losing context */
272 tst r4, #WFI_FLAG_SELF_REFRESH
273 beq emif_skip_exit_sr_abt
231
274
275 adr r9, am43xx_emif_sram_table
276 ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
277 blx r1
278
279emif_skip_exit_sr_abt:
232 /* Let the suspend code know about the abort */
233 mov r0, #1
234 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
235ENDPROC(am43xx_do_wfi)
236
237 .align
238ENTRY(am43xx_resume_offset)
239 .word . - am43xx_do_wfi

--- 151 unchanged lines hidden ---
280 /* Let the suspend code know about the abort */
281 mov r0, #1
282 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
283ENDPROC(am43xx_do_wfi)
284
285 .align
286ENTRY(am43xx_resume_offset)
287 .word . - am43xx_do_wfi

--- 151 unchanged lines hidden ---