sleep34xx.S (b4b36fd94e4ca99b3258ff24c2c58cdde67085e0) sleep34xx.S (fe360e1c8693bca175338da4c53078b0be807c52)
1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007
5 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com>
7 *
8 * (C) Copyright 2004

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29#include <plat/sram.h>
30#include <mach/io.h>
31
32#include "cm.h"
33#include "prm.h"
34#include "sdrc.h"
35#include "control.h"
36
1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007
5 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com>
7 *
8 * (C) Copyright 2004

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29#include <plat/sram.h>
30#include <mach/io.h>
31
32#include "cm.h"
33#include "prm.h"
34#include "sdrc.h"
35#include "control.h"
36
37#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c
38
39#define PM_PREPWSTST_CORE_P 0x48306AE8
37/*
38 * Registers access definitions
39 */
40#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
41#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
42 (SDRC_SCRATCHPAD_SEM_OFFS)
43#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
44 OMAP3430_PM_PREPWSTST
40#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
41#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
42#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
45#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
46#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
47#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
43#define SRAM_BASE_P 0x40200000
44#define CONTROL_STAT 0x480022F0
45#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
46 + OMAP36XX_CONTROL_MEM_RTA_CTRL)
47#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
48 * available */
49#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
50 + SCRATCHPAD_MEM_OFFS)
48#define SRAM_BASE_P OMAP3_SRAM_PA
49#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
50#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
51 OMAP36XX_CONTROL_MEM_RTA_CTRL)
52
53/* Move this as correct place is available */
54#define SCRATCHPAD_MEM_OFFS 0x310
55#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
56 OMAP343X_CONTROL_MEM_WKUP +\
57 SCRATCHPAD_MEM_OFFS)
51#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
52#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
53#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
54#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
55#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
56#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
57#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
58#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)

--- 618 unchanged lines hidden --- 		58#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
59#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
60#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
61#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
62#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
63#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
64#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
65#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)

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