sleep34xx.S (9d93b8a2c8c78972f0a3d15a820288dbb3968bf2) sleep34xx.S (458e999eb14a301d4176783c8fcb277f5d009b4e)
1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007
5 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com>
7 *
8 * (C) Copyright 2004

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40#define PM_PREPWSTST_CORE_P 0x48306AE8
41#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
42 OMAP3430_PM_PREPWSTST)
43#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
44#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
45#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
46#define SRAM_BASE_P 0x40200000
47#define CONTROL_STAT 0x480022F0
1/*
2 * linux/arch/arm/mach-omap2/sleep.S
3 *
4 * (C) Copyright 2007
5 * Texas Instruments
6 * Karthik Dasu <karthik-dp@ti.com>
7 *
8 * (C) Copyright 2004

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40#define PM_PREPWSTST_CORE_P 0x48306AE8
41#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
42 OMAP3430_PM_PREPWSTST)
43#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
44#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
45#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
46#define SRAM_BASE_P 0x40200000
47#define CONTROL_STAT 0x480022F0
48#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
49 + OMAP36XX_CONTROL_MEM_RTA_CTRL)
48#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
49 * available */
50#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
51 + SCRATCHPAD_MEM_OFFS)
52#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
53#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
54#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
55#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)

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94 .text
95/* Function call to get the restore pointer for resume from OFF */
96ENTRY(get_restore_pointer)
97 stmfd sp!, {lr} @ save registers on stack
98 adr r0, restore
99 ldmfd sp!, {pc} @ restore regs and return
100ENTRY(get_restore_pointer_sz)
101 .word . - get_restore_pointer
50#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
51 * available */
52#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
53 + SCRATCHPAD_MEM_OFFS)
54#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
55#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
56#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
57#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)

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96 .text
97/* Function call to get the restore pointer for resume from OFF */
98ENTRY(get_restore_pointer)
99 stmfd sp!, {lr} @ save registers on stack
100 adr r0, restore
101 ldmfd sp!, {pc} @ restore regs and return
102ENTRY(get_restore_pointer_sz)
103 .word . - get_restore_pointer
104 .text
105/* Function call to get the restore pointer for 3630 resume from OFF */
106ENTRY(get_omap3630_restore_pointer)
107 stmfd sp!, {lr} @ save registers on stack
108 adr r0, restore_3630
109 ldmfd sp!, {pc} @ restore regs and return
110ENTRY(get_omap3630_restore_pointer_sz)
111 .word . - get_omap3630_restore_pointer
102
103 .text
104/* Function call to get the restore pointer for for ES3 to resume from OFF */
105ENTRY(get_es3_restore_pointer)
106 stmfd sp!, {lr} @ save registers on stack
107 adr r0, restore_es3
108 ldmfd sp!, {pc} @ restore regs and return
109ENTRY(get_es3_restore_pointer_sz)

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241 mov r2, r2, ror #2
242copy_to_sram:
243 ldmia r0!, {r3} @ val = *src
244 stmia r1!, {r3} @ *dst = val
245 subs r2, r2, #0x1 @ num_words--
246 bne copy_to_sram
247 ldr r1, sram_base
248 blx r1
112
113 .text
114/* Function call to get the restore pointer for for ES3 to resume from OFF */
115ENTRY(get_es3_restore_pointer)
116 stmfd sp!, {lr} @ save registers on stack
117 adr r0, restore_es3
118 ldmfd sp!, {pc} @ restore regs and return
119ENTRY(get_es3_restore_pointer_sz)

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251 mov r2, r2, ror #2
252copy_to_sram:
253 ldmia r0!, {r3} @ val = *src
254 stmia r1!, {r3} @ *dst = val
255 subs r2, r2, #0x1 @ num_words--
256 bne copy_to_sram
257 ldr r1, sram_base
258 blx r1
259 b restore
260
261restore_3630:
262 /*b restore_es3630*/ @ Enable to debug restore code
263 ldr r1, pm_prepwstst_core_p
264 ldr r2, [r1]
265 and r2, r2, #0x3
266 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
267 bne restore
268 /* Disable RTA before giving control */
269 ldr r1, control_mem_rta
270 mov r2, #OMAP36XX_RTA_DISABLE
271 str r2, [r1]
272 /* Fall thru for the remaining logic */
249restore:
250 /* b restore*/ @ Enable to debug restore code
251 /* Check what was the reason for mpu reset and store the reason in r9*/
252 /* 1 - Only L1 and logic lost */
253 /* 2 - Only L2 lost - In this case, we wont be here */
254 /* 3 - Both L1 and L2 lost */
255 ldr r1, pm_pwstctrl_mpu
256 ldr r2, [r1]

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646table_index_mask:
647 .word 0xFFF00000
648table_entry:
649 .word 0x00000C02
650cache_pred_disable_mask:
651 .word 0xFFFFE7FB
652control_stat:
653 .word CONTROL_STAT
273restore:
274 /* b restore*/ @ Enable to debug restore code
275 /* Check what was the reason for mpu reset and store the reason in r9*/
276 /* 1 - Only L1 and logic lost */
277 /* 2 - Only L2 lost - In this case, we wont be here */
278 /* 3 - Both L1 and L2 lost */
279 ldr r1, pm_pwstctrl_mpu
280 ldr r2, [r1]

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670table_index_mask:
671 .word 0xFFF00000
672table_entry:
673 .word 0x00000C02
674cache_pred_disable_mask:
675 .word 0xFFFFE7FB
676control_stat:
677 .word CONTROL_STAT
678control_mem_rta:
679 .word CONTROL_MEM_RTA_CTRL
654kernel_flush:
655 .word v7_flush_dcache_all
656 /*
657 * When exporting to userspace while the counters are in SRAM,
658 * these 2 words need to be at the end to facilitate retrival!
659 */
660kick_counter:
661 .word 0
662wait_dll_lock_counter:
663 .word 0
664ENTRY(omap34xx_cpu_suspend_sz)
665 .word . - omap34xx_cpu_suspend
680kernel_flush:
681 .word v7_flush_dcache_all
682 /*
683 * When exporting to userspace while the counters are in SRAM,
684 * these 2 words need to be at the end to facilitate retrival!
685 */
686kick_counter:
687 .word 0
688wait_dll_lock_counter:
689 .word 0
690ENTRY(omap34xx_cpu_suspend_sz)
691 .word . - omap34xx_cpu_suspend