| sleep24xx.S (f43dc23d5ea91fca257be02138a255f02d98e806) | sleep24xx.S (b6338bdc8305b27688a7feb8689e4ccfd42f0292) |
|---|---|
| 1/* 2 * linux/arch/arm/mach-omap2/sleep.S 3 * 4 * (C) Copyright 2004 5 * Texas Instruments, <www.ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * 8 * (C) Copyright 2006 Nokia Corporation --- 33 unchanged lines hidden (view full) --- 42 * Forces OMAP into idle state 43 * 44 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI 45 * for normal idles. 46 * 47 * Note: This code get's copied to internal SRAM at boot. When the OMAP 48 * wakes up it continues execution at the point it went to sleep. 49 */ | 1/* 2 * linux/arch/arm/mach-omap2/sleep.S 3 * 4 * (C) Copyright 2004 5 * Texas Instruments, <www.ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com> 7 * 8 * (C) Copyright 2006 Nokia Corporation --- 33 unchanged lines hidden (view full) --- 42 * Forces OMAP into idle state 43 * 44 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI 45 * for normal idles. 46 * 47 * Note: This code get's copied to internal SRAM at boot. When the OMAP 48 * wakes up it continues execution at the point it went to sleep. 49 */ |
| 50 .align 3 |
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| 50ENTRY(omap24xx_idle_loop_suspend) 51 stmfd sp!, {r0, lr} @ save registers on stack 52 mov r0, #0 @ clear for mcr setup 53 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 54 ldmfd sp!, {r0, pc} @ restore regs and return 55 56ENTRY(omap24xx_idle_loop_suspend_sz) 57 .word . - omap24xx_idle_loop_suspend --- 19 unchanged lines hidden (view full) --- 77 * To work around this the code will switch to the 32kHz source prior to sleep. 78 * Post sleep we will shift back to using the DPLL. Apparently, 79 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait 80 * 3x12MHz + 3x32kHz clocks for a full switch. 81 * 82 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored 83 * at wake 84 */ | 51ENTRY(omap24xx_idle_loop_suspend) 52 stmfd sp!, {r0, lr} @ save registers on stack 53 mov r0, #0 @ clear for mcr setup 54 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 55 ldmfd sp!, {r0, pc} @ restore regs and return 56 57ENTRY(omap24xx_idle_loop_suspend_sz) 58 .word . - omap24xx_idle_loop_suspend --- 19 unchanged lines hidden (view full) --- 78 * To work around this the code will switch to the 32kHz source prior to sleep. 79 * Post sleep we will shift back to using the DPLL. Apparently, 80 * CM_IDLEST_CLKGEN does not reflect the full clock change so you need to wait 81 * 3x12MHz + 3x32kHz clocks for a full switch. 82 * 83 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored 84 * at wake 85 */ |
| 86 .align 3 |
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| 85ENTRY(omap24xx_cpu_suspend) 86 stmfd sp!, {r0 - r12, lr} @ save registers on stack 87 mov r3, #0x0 @ clear for mcr call 88 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 89 nop 90 nop 91 ldr r4, [r2] @ read SDRC_POWER 92 orr r4, r4, #0x40 @ enable self refresh on idle req --- 32 unchanged lines hidden --- | 87ENTRY(omap24xx_cpu_suspend) 88 stmfd sp!, {r0 - r12, lr} @ save registers on stack 89 mov r3, #0x0 @ clear for mcr call 90 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 91 nop 92 nop 93 ldr r4, [r2] @ read SDRC_POWER 94 orr r4, r4, #0x40 @ enable self refresh on idle req --- 32 unchanged lines hidden --- |