prm.h (2457552d1e6f3183cd93f81c49a8da5fe8bb0e42) prm.h (3790300903e6a98ce5f5391f4d435959266f79e7)
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
6 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2009 Nokia Corporation

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19#define OMAP2420_PRM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21#define OMAP2430_PRM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23#define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
1#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
2#define __ARCH_ARM_MACH_OMAP2_PRM_H
3
4/*
5 * OMAP2/3 Power/Reset Management (PRM) register definitions
6 *
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2009 Nokia Corporation

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19#define OMAP2420_PRM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
21#define OMAP2430_PRM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
23#define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25#define OMAP44XX_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
27#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \
28 OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg))
27
28#include "prm44xx.h"
29
30/*
31 * Architecture-specific global PRM registers
32 * Use __raw_{read,write}l() with these registers.
33 *
34 * With a few exceptions, these are the register names beginning with

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172 * With a few exceptions, these are the register names beginning with
173 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
174 * and IRQENABLE bits.)
175 *
176 */
177
178/* Registers appearing on both 24xx and 34xx */
179
29
30#include "prm44xx.h"
31
32/*
33 * Architecture-specific global PRM registers
34 * Use __raw_{read,write}l() with these registers.
35 *
36 * With a few exceptions, these are the register names beginning with

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174 * With a few exceptions, these are the register names beginning with
175 * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS
176 * and IRQENABLE bits.)
177 *
178 */
179
180/* Registers appearing on both 24xx and 34xx */
181
180#define RM_RSTCTRL 0x0050
181#define RM_RSTTIME 0x0054
182#define RM_RSTST 0x0058
182#define OMAP2_RM_RSTCTRL 0x0050
183#define OMAP2_RM_RSTTIME 0x0054
184#define OMAP2_RM_RSTST 0x0058
185#define OMAP2_PM_PWSTCTRL 0x00e0
186#define OMAP2_PM_PWSTST 0x00e4
183
184#define PM_WKEN 0x00a0
185#define PM_WKEN1 PM_WKEN
186#define PM_WKST 0x00b0
187#define PM_WKST1 PM_WKST
188#define PM_WKDEP 0x00c8
189#define PM_EVGENCTRL 0x00d4
190#define PM_EVGENONTIM 0x00d8
191#define PM_EVGENOFFTIM 0x00dc
187
188#define PM_WKEN 0x00a0
189#define PM_WKEN1 PM_WKEN
190#define PM_WKST 0x00b0
191#define PM_WKST1 PM_WKST
192#define PM_WKDEP 0x00c8
193#define PM_EVGENCTRL 0x00d4
194#define PM_EVGENONTIM 0x00d8
195#define PM_EVGENOFFTIM 0x00dc
192#define PM_PWSTCTRL 0x00e0
193#define PM_PWSTST 0x00e4
194
195/* Omap2 specific registers */
196#define OMAP24XX_PM_WKEN2 0x00a4
197#define OMAP24XX_PM_WKST2 0x00b4
198
199#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
200#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
201#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8

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213#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
214#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
215
216#define OMAP3430_PM_PREPWSTST 0x00e8
217
218#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
219#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
220
196
197/* Omap2 specific registers */
198#define OMAP24XX_PM_WKEN2 0x00a4
199#define OMAP24XX_PM_WKST2 0x00b4
200
201#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
202#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
203#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8

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215#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
216#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
217
218#define OMAP3430_PM_PREPWSTST 0x00e8
219
220#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
221#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
222
223/* Omap4 specific registers */
224#define OMAP4_RM_RSTCTRL 0x0000
225#define OMAP4_RM_RSTTIME 0x0004
226#define OMAP4_RM_RSTST 0x0008
227#define OMAP4_PM_PWSTCTRL 0x0000
228#define OMAP4_PM_PWSTST 0x0004
221
229
230
222#ifndef __ASSEMBLER__
223
224/* Power/reset management domain register get/set */
225extern u32 prm_read_mod_reg(s16 module, u16 idx);
226extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
227extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
228
229/* Read-modify-write bits in a PRM register (by domain) */

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232
233/* Power/reset management domain register get/set */
234extern u32 prm_read_mod_reg(s16 module, u16 idx);
235extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
236extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
237
238/* Read-modify-write bits in a PRM register (by domain) */

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