io.c (688d794c4c3f8b08c814381ee2edd3ede5856056) io.c (1348bbf942ebf21db7ff235f9bbdf9cd36be3ffe)
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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266 .type = MT_DEVICE,
267 },
268 {
269 .virtual = L4_PER_54XX_VIRT,
270 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
271 .length = L4_PER_54XX_SIZE,
272 .type = MT_DEVICE,
273 },
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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266 .type = MT_DEVICE,
267 },
268 {
269 .virtual = L4_PER_54XX_VIRT,
270 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
271 .length = L4_PER_54XX_SIZE,
272 .type = MT_DEVICE,
273 },
274#ifdef CONFIG_OMAP4_ERRATA_I688
275 {
276 .virtual = OMAP4_SRAM_VA,
277 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
278 .length = PAGE_SIZE,
279 .type = MT_MEMORY_SO,
280 },
281#endif
274};
275#endif
276
277#ifdef CONFIG_SOC_OMAP2420
278void __init omap242x_map_io(void)
279{
280 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
281 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));

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318 omap_barriers_init();
319}
320#endif
321
322#ifdef CONFIG_SOC_OMAP5
323void __init omap5_map_io(void)
324{
325 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
282};
283#endif
284
285#ifdef CONFIG_SOC_OMAP2420
286void __init omap242x_map_io(void)
287{
288 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
289 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));

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326 omap_barriers_init();
327}
328#endif
329
330#ifdef CONFIG_SOC_OMAP5
331void __init omap5_map_io(void)
332{
333 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
334 omap_barriers_init();
326}
327#endif
328/*
329 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
330 *
331 * Sets the CORE DPLL3 M2 divider to the same value that it's at
332 * currently. This has the effect of setting the SDRC SDRAM AC timing
333 * registers to the values currently defined by the kernel. Currently

--- 301 unchanged lines hidden --- 		335}
336#endif
337/*
338 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
339 *
340 * Sets the CORE DPLL3 M2 divider to the same value that it's at
341 * currently. This has the effect of setting the SDRC SDRAM AC timing
342 * registers to the values currently defined by the kernel. Currently

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