| Kconfig (d608d71cd6d19792487d08333d63c7ff20294694) | Kconfig (1348bbf942ebf21db7ff235f9bbdf9cd36be3ffe) |
|---|---|
| 1config ARCH_OMAP 2 bool 3 4config ARCH_OMAP2PLUS 5 bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7) 6 select ARCH_HAS_CPUFREQ 7 select ARCH_HAS_HOLES_MEMORYMODEL 8 select ARCH_OMAP --- 394 unchanged lines hidden (view full) --- 403 access SDRAM during CORE DVFS, select Y here. This should boost 404 SDRAM performance at lower CORE OPPs. There are relatively few 405 users who will wish to say yes at this point - almost everyone will 406 wish to say no. Selecting yes without understanding what is 407 going on could result in system crashes; 408 409config OMAP4_ERRATA_I688 410 bool "OMAP4 errata: Async Bridge Corruption" | 1config ARCH_OMAP 2 bool 3 4config ARCH_OMAP2PLUS 5 bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7) 6 select ARCH_HAS_CPUFREQ 7 select ARCH_HAS_HOLES_MEMORYMODEL 8 select ARCH_OMAP --- 394 unchanged lines hidden (view full) --- 403 access SDRAM during CORE DVFS, select Y here. This should boost 404 SDRAM performance at lower CORE OPPs. There are relatively few 405 users who will wish to say yes at this point - almost everyone will 406 wish to say no. Selecting yes without understanding what is 407 going on could result in system crashes; 408 409config OMAP4_ERRATA_I688 410 bool "OMAP4 errata: Async Bridge Corruption" |
| 411 depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM | 411 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM |
| 412 select ARCH_HAS_BARRIERS 413 help 414 If a data is stalled inside asynchronous bridge because of back 415 pressure, it may be accepted multiple times, creating pointer 416 misalignment that will corrupt next transfers on that data path 417 until next reset of the system (No recovery procedure once the 418 issue is hit, the path remains consistently broken). Async bridge 419 can be found on path between MPU to EMIF and MPU to L3 interconnect. --- 13 unchanged lines hidden --- | 412 select ARCH_HAS_BARRIERS 413 help 414 If a data is stalled inside asynchronous bridge because of back 415 pressure, it may be accepted multiple times, creating pointer 416 misalignment that will corrupt next transfers on that data path 417 until next reset of the system (No recovery procedure once the 418 issue is hit, the path remains consistently broken). Async bridge 419 can be found on path between MPU to EMIF and MPU to L3 interconnect. --- 13 unchanged lines hidden --- |