| Kconfig (734d1ece37fbf3d2ddfc71bc6c69e0fe35f02542) | Kconfig (a62a6e98c370ccca37d353a5f763b532411a4c14) |
|---|---|
| 1if ARCH_OMAP2PLUS 2 3menu "TI OMAP2/3/4 Specific Features" 4 5config ARCH_OMAP2PLUS_TYPICAL 6 bool "Typical OMAP configuration" 7 default y 8 select AEABI --- 383 unchanged lines hidden (view full) --- 392 access SDRAM during CORE DVFS, select Y here. This should boost 393 SDRAM performance at lower CORE OPPs. There are relatively few 394 users who will wish to say yes at this point - almost everyone will 395 wish to say no. Selecting yes without understanding what is 396 going on could result in system crashes; 397 398config OMAP4_ERRATA_I688 399 bool "OMAP4 errata: Async Bridge Corruption" | 1if ARCH_OMAP2PLUS 2 3menu "TI OMAP2/3/4 Specific Features" 4 5config ARCH_OMAP2PLUS_TYPICAL 6 bool "Typical OMAP configuration" 7 default y 8 select AEABI --- 383 unchanged lines hidden (view full) --- 392 access SDRAM during CORE DVFS, select Y here. This should boost 393 SDRAM performance at lower CORE OPPs. There are relatively few 394 users who will wish to say yes at this point - almost everyone will 395 wish to say no. Selecting yes without understanding what is 396 going on could result in system crashes; 397 398config OMAP4_ERRATA_I688 399 bool "OMAP4 errata: Async Bridge Corruption" |
| 400 depends on ARCH_OMAP4 | 400 depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM |
| 401 select ARCH_HAS_BARRIERS 402 help 403 If a data is stalled inside asynchronous bridge because of back 404 pressure, it may be accepted multiple times, creating pointer 405 misalignment that will corrupt next transfers on that data path 406 until next reset of the system (No recovery procedure once the 407 issue is hit, the path remains consistently broken). Async bridge 408 can be found on path between MPU to EMIF and MPU to L3 interconnect. --- 13 unchanged lines hidden --- | 401 select ARCH_HAS_BARRIERS 402 help 403 If a data is stalled inside asynchronous bridge because of back 404 pressure, it may be accepted multiple times, creating pointer 405 misalignment that will corrupt next transfers on that data path 406 until next reset of the system (No recovery procedure once the 407 issue is hit, the path remains consistently broken). Async bridge 408 can be found on path between MPU to EMIF and MPU to L3 interconnect. --- 13 unchanged lines hidden --- |