| Kconfig (3642a0a2c7d2d1949988d0fd004a8039c1f3d02f) | Kconfig (137d105d50f6e6c373c1aa759f59045e6239cf66) |
|---|---|
| 1if ARCH_OMAP2PLUS 2 3menu "TI OMAP2/3/4 Specific Features" 4 5config ARCH_OMAP2PLUS_TYPICAL 6 bool "Typical OMAP configuration" 7 default y 8 select AEABI --- 11 unchanged lines hidden (view full) --- 20 help 21 Compile a kernel suitable for booting most boards 22 23config ARCH_OMAP2 24 bool "TI OMAP2" 25 depends on ARCH_OMAP2PLUS 26 default y 27 select CPU_V6 | 1if ARCH_OMAP2PLUS 2 3menu "TI OMAP2/3/4 Specific Features" 4 5config ARCH_OMAP2PLUS_TYPICAL 6 bool "Typical OMAP configuration" 7 default y 8 select AEABI --- 11 unchanged lines hidden (view full) --- 20 help 21 Compile a kernel suitable for booting most boards 22 23config ARCH_OMAP2 24 bool "TI OMAP2" 25 depends on ARCH_OMAP2PLUS 26 default y 27 select CPU_V6 |
| 28 select MULTI_IRQ_HANDLER |
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| 28 29config ARCH_OMAP3 30 bool "TI OMAP3" 31 depends on ARCH_OMAP2PLUS 32 default y 33 select CPU_V7 34 select USB_ARCH_HAS_EHCI 35 select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 36 select ARCH_HAS_OPP 37 select PM_OPP if PM 38 select ARM_CPU_SUSPEND if PM | 29 30config ARCH_OMAP3 31 bool "TI OMAP3" 32 depends on ARCH_OMAP2PLUS 33 default y 34 select CPU_V7 35 select USB_ARCH_HAS_EHCI 36 select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 37 select ARCH_HAS_OPP 38 select PM_OPP if PM 39 select ARM_CPU_SUSPEND if PM |
| 40 select MULTI_IRQ_HANDLER |
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| 39 40config ARCH_OMAP4 41 bool "TI OMAP4" 42 default y 43 depends on ARCH_OMAP2PLUS 44 select CPU_V7 45 select ARM_GIC 46 select LOCAL_TIMERS if SMP --- 299 unchanged lines hidden (view full) --- 346 help 347 If you know that none of your system initiators will attempt to 348 access SDRAM during CORE DVFS, select Y here. This should boost 349 SDRAM performance at lower CORE OPPs. There are relatively few 350 users who will wish to say yes at this point - almost everyone will 351 wish to say no. Selecting yes without understanding what is 352 going on could result in system crashes; 353 | 41 42config ARCH_OMAP4 43 bool "TI OMAP4" 44 default y 45 depends on ARCH_OMAP2PLUS 46 select CPU_V7 47 select ARM_GIC 48 select LOCAL_TIMERS if SMP --- 299 unchanged lines hidden (view full) --- 348 help 349 If you know that none of your system initiators will attempt to 350 access SDRAM during CORE DVFS, select Y here. This should boost 351 SDRAM performance at lower CORE OPPs. There are relatively few 352 users who will wish to say yes at this point - almost everyone will 353 wish to say no. Selecting yes without understanding what is 354 going on could result in system crashes; 355 |
| 356config OMAP4_ERRATA_I688 357 bool "OMAP4 errata: Async Bridge Corruption" 358 depends on ARCH_OMAP4 359 select ARCH_HAS_BARRIERS 360 help 361 If a data is stalled inside asynchronous bridge because of back 362 pressure, it may be accepted multiple times, creating pointer 363 misalignment that will corrupt next transfers on that data path 364 until next reset of the system (No recovery procedure once the 365 issue is hit, the path remains consistently broken). Async bridge 366 can be found on path between MPU to EMIF and MPU to L3 interconnect. 367 This situation can happen only when the idle is initiated by a 368 Master Request Disconnection (which is trigged by software when 369 executing WFI on CPU). 370 The work-around for this errata needs all the initiators connected 371 through async bridge must ensure that data path is properly drained 372 before issuing WFI. This condition will be met if one Strongly ordered 373 access is performed to the target right before executing the WFI. 374 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. 375 IO barrier ensure that there is no synchronisation loss on initiators 376 operating on both interconnect port simultaneously. |
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| 354endmenu 355 356endif | 377endmenu 378 379endif |