| Kconfig (188933ac139a6f8ab06cad369bd0200af947b00d) | Kconfig (209431eff8afb928d72200c79153165c7d860ca0) |
|---|---|
| 1menu "TI OMAP/AM/DM/DRA Family" 2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 3 4config ARCH_OMAP2 5 bool "TI OMAP2" 6 depends on ARCH_MULTI_V6 7 select ARCH_OMAP2PLUS 8 select CPU_V6 --- 55 unchanged lines hidden (view full) --- 64config SOC_DRA7XX 65 bool "TI DRA7XX" 66 depends on ARCH_MULTI_V7 67 select ARCH_OMAP2PLUS 68 select ARM_CPU_SUSPEND if PM 69 select ARM_GIC 70 select HAVE_ARM_ARCH_TIMER 71 select IRQ_CROSSBAR | 1menu "TI OMAP/AM/DM/DRA Family" 2 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 3 4config ARCH_OMAP2 5 bool "TI OMAP2" 6 depends on ARCH_MULTI_V6 7 select ARCH_OMAP2PLUS 8 select CPU_V6 --- 55 unchanged lines hidden (view full) --- 64config SOC_DRA7XX 65 bool "TI DRA7XX" 66 depends on ARCH_MULTI_V7 67 select ARCH_OMAP2PLUS 68 select ARM_CPU_SUSPEND if PM 69 select ARM_GIC 70 select HAVE_ARM_ARCH_TIMER 71 select IRQ_CROSSBAR |
| 72 select ARM_ERRATA_798181 if SMP |
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| 72 73config ARCH_OMAP2PLUS 74 bool 75 select ARCH_HAS_BANDGAP 76 select ARCH_HAS_HOLES_MEMORYMODEL 77 select ARCH_OMAP 78 select ARCH_REQUIRE_GPIOLIB 79 select CLKSRC_MMIO --- 193 unchanged lines hidden (view full) --- 273 help 274 If you know that none of your system initiators will attempt to 275 access SDRAM during CORE DVFS, select Y here. This should boost 276 SDRAM performance at lower CORE OPPs. There are relatively few 277 users who will wish to say yes at this point - almost everyone will 278 wish to say no. Selecting yes without understanding what is 279 going on could result in system crashes; 280 | 73 74config ARCH_OMAP2PLUS 75 bool 76 select ARCH_HAS_BANDGAP 77 select ARCH_HAS_HOLES_MEMORYMODEL 78 select ARCH_OMAP 79 select ARCH_REQUIRE_GPIOLIB 80 select CLKSRC_MMIO --- 193 unchanged lines hidden (view full) --- 274 help 275 If you know that none of your system initiators will attempt to 276 access SDRAM during CORE DVFS, select Y here. This should boost 277 SDRAM performance at lower CORE OPPs. There are relatively few 278 users who will wish to say yes at this point - almost everyone will 279 wish to say no. Selecting yes without understanding what is 280 going on could result in system crashes; 281 |
| 281config OMAP4_ERRATA_I688 282 bool "OMAP4 errata: Async Bridge Corruption" 283 depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM 284 select ARCH_HAS_BARRIERS 285 help 286 If a data is stalled inside asynchronous bridge because of back 287 pressure, it may be accepted multiple times, creating pointer 288 misalignment that will corrupt next transfers on that data path 289 until next reset of the system (No recovery procedure once the 290 issue is hit, the path remains consistently broken). Async bridge 291 can be found on path between MPU to EMIF and MPU to L3 interconnect. 292 This situation can happen only when the idle is initiated by a 293 Master Request Disconnection (which is trigged by software when 294 executing WFI on CPU). 295 The work-around for this errata needs all the initiators connected 296 through async bridge must ensure that data path is properly drained 297 before issuing WFI. This condition will be met if one Strongly ordered 298 access is performed to the target right before executing the WFI. 299 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. 300 IO barrier ensure that there is no synchronisation loss on initiators 301 operating on both interconnect port simultaneously. | |
| 302endmenu 303 304endif 305 306endmenu | 282endmenu 283 284endif 285 286endmenu |