serial.c (ea9b395fe20ac74be788f415af2622ac8f0c35c7) serial.c (30ff720b40ba64b0e9c8974673b95970e68503ac)
1/*
2 * linux/arch/arm/mach-omap1/id.c
3 *
4 * OMAP1 CPU identification code
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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141 }
142
143 switch (i) {
144 case 0:
145 uart1_ck = clk_get(NULL, "uart1_ck");
146 if (IS_ERR(uart1_ck))
147 printk("Could not get uart1_ck\n");
148 else {
1/*
2 * linux/arch/arm/mach-omap1/id.c
3 *
4 * OMAP1 CPU identification code
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

--- 132 unchanged lines hidden (view full) ---

141 }
142
143 switch (i) {
144 case 0:
145 uart1_ck = clk_get(NULL, "uart1_ck");
146 if (IS_ERR(uart1_ck))
147 printk("Could not get uart1_ck\n");
148 else {
149 clk_use(uart1_ck);
149 clk_enable(uart1_ck);
150 if (cpu_is_omap1510())
151 clk_set_rate(uart1_ck, 12000000);
152 }
153 if (cpu_is_omap1510()) {
154 omap_cfg_reg(UART1_TX);
155 omap_cfg_reg(UART1_RTS);
156 if (machine_is_omap_innovator()) {
157 reg = fpga_read(OMAP1510_FPGA_POWER);
158 reg |= OMAP1510_FPGA_PCR_COM1_EN;
159 fpga_write(reg, OMAP1510_FPGA_POWER);
160 udelay(10);
161 }
162 }
163 break;
164 case 1:
165 uart2_ck = clk_get(NULL, "uart2_ck");
166 if (IS_ERR(uart2_ck))
167 printk("Could not get uart2_ck\n");
168 else {
150 if (cpu_is_omap1510())
151 clk_set_rate(uart1_ck, 12000000);
152 }
153 if (cpu_is_omap1510()) {
154 omap_cfg_reg(UART1_TX);
155 omap_cfg_reg(UART1_RTS);
156 if (machine_is_omap_innovator()) {
157 reg = fpga_read(OMAP1510_FPGA_POWER);
158 reg |= OMAP1510_FPGA_PCR_COM1_EN;
159 fpga_write(reg, OMAP1510_FPGA_POWER);
160 udelay(10);
161 }
162 }
163 break;
164 case 1:
165 uart2_ck = clk_get(NULL, "uart2_ck");
166 if (IS_ERR(uart2_ck))
167 printk("Could not get uart2_ck\n");
168 else {
169 clk_use(uart2_ck);
169 clk_enable(uart2_ck);
170 if (cpu_is_omap1510())
171 clk_set_rate(uart2_ck, 12000000);
172 else
173 clk_set_rate(uart2_ck, 48000000);
174 }
175 if (cpu_is_omap1510()) {
176 omap_cfg_reg(UART2_TX);
177 omap_cfg_reg(UART2_RTS);

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183 }
184 }
185 break;
186 case 2:
187 uart3_ck = clk_get(NULL, "uart3_ck");
188 if (IS_ERR(uart3_ck))
189 printk("Could not get uart3_ck\n");
190 else {
170 if (cpu_is_omap1510())
171 clk_set_rate(uart2_ck, 12000000);
172 else
173 clk_set_rate(uart2_ck, 48000000);
174 }
175 if (cpu_is_omap1510()) {
176 omap_cfg_reg(UART2_TX);
177 omap_cfg_reg(UART2_RTS);

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183 }
184 }
185 break;
186 case 2:
187 uart3_ck = clk_get(NULL, "uart3_ck");
188 if (IS_ERR(uart3_ck))
189 printk("Could not get uart3_ck\n");
190 else {
191 clk_use(uart3_ck);
191 clk_enable(uart3_ck);
192 if (cpu_is_omap1510())
193 clk_set_rate(uart3_ck, 12000000);
194 }
195 if (cpu_is_omap1510()) {
196 omap_cfg_reg(UART3_TX);
197 omap_cfg_reg(UART3_RX);
198 }
199 break;

--- 89 unchanged lines hidden --- 		192 if (cpu_is_omap1510())
193 clk_set_rate(uart3_ck, 12000000);
194 }
195 if (cpu_is_omap1510()) {
196 omap_cfg_reg(UART3_TX);
197 omap_cfg_reg(UART3_RX);
198 }
199 break;

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