io.c (71f2c153755442c05d15cd025484f676a5f3541f) io.c (7b88e62f5d219a86d81bdf4388012c97dc42e8f8)
1/*
2 * linux/arch/arm/mach-omap1/io.c
3 *
4 * OMAP1 I/O mapping code
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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80 .pfn = __phys_to_pfn(OMAP16XX_DSPREG_START),
81 .length = OMAP16XX_DSPREG_SIZE,
82 .type = MT_DEVICE
83 }
84};
85#endif
86
87/*
1/*
2 * linux/arch/arm/mach-omap1/io.c
3 *
4 * OMAP1 I/O mapping code
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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80 .pfn = __phys_to_pfn(OMAP16XX_DSPREG_START),
81 .length = OMAP16XX_DSPREG_SIZE,
82 .type = MT_DEVICE
83 }
84};
85#endif
86
87/*
88 * Maps common IO regions for omap1. This should only get called from
89 * board specific init.
88 * Maps common IO regions for omap1
90 */
89 */
91void __init omap1_map_common_io(void)
90static void __init omap1_map_common_io(void)
92{
93 iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
91{
92 iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
93}
94
94
95 /* Normally devicemaps_init() would flush caches and tlb after
96 * mdesc->map_io(), but we must also do it here because of the CPU
97 * revision check below.
98 */
99 local_flush_tlb_all();
100 flush_cache_all();
101
102 /* We want to check CPU revision early for cpu_is_omapxxxx() macros.
103 * IO space mapping must be initialized before we can do that.
104 */
105 omap_check_revision();
106
107#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
95#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
108 if (cpu_is_omap7xx()) {
109 iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
110 }
96void __init omap7xx_map_io(void)
97{
98 omap1_map_common_io();
99 iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
100}
111#endif
101#endif
102
112#ifdef CONFIG_ARCH_OMAP15XX
103#ifdef CONFIG_ARCH_OMAP15XX
113 if (cpu_is_omap15xx()) {
114 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
115 }
104void __init omap15xx_map_io(void)
105{
106 omap1_map_common_io();
107 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
108}
116#endif
109#endif
110
117#if defined(CONFIG_ARCH_OMAP16XX)
111#if defined(CONFIG_ARCH_OMAP16XX)
118 if (cpu_is_omap16xx()) {
119 iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
120 }
112void __init omap16xx_map_io(void)
113{
114 omap1_map_common_io();
115 iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
116}
121#endif
122
117#endif
118
123 omap_sram_init();
124 omap_init_consistent_dma_size();
125}
126
127/*
119/*
128 * Common low-level hardware init for omap1. This should only get called from
129 * board specific init.
120 * Common low-level hardware init for omap1.
130 */
121 */
131void __init omap1_init_common_hw(void)
122void omap1_init_early(void)
132{
123{
124 omap_check_revision();
125
133 /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
134 * on a Posted Write in the TIPB Bridge".
135 */
136 omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
137 omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
138
139 /* Must init clocks early to assure that timer interrupt works
140 */
141 omap1_clk_init();
126 /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
127 * on a Posted Write in the TIPB Bridge".
128 */
129 omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL);
130 omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL);
131
132 /* Must init clocks early to assure that timer interrupt works
133 */
134 omap1_clk_init();
142
143 omap1_mux_init();
135 omap1_mux_init();
136 omap_sram_init();
144}
145
146/*
147 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
148 */
149
150u8 omap_readb(u32 pa)
151{

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138
139/*
140 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
141 */
142
143u8 omap_readb(u32 pa)
144{

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