clock.c (d8a382d2662822248a97ce9d670b90e68aefbd3a) clock.c (fb2fc9204f8ce060d239ab41f09cf6fc6de5ad4b)
1/*
2 * linux/arch/arm/mach-omap1/clock.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 *
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
1/*
2 * linux/arch/arm/mach-omap1/clock.c
3 *
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 *
7 * Modified to use omap shared clock framework by
8 * Tony Lindgren <tony@atomide.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21
22#include <asm/mach-types.h>

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29#include <plat/clkdev_omap.h>
30
31#include "clock.h"
32#include "opp.h"
33
34__u32 arm_idlect1_mask;
35struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
36
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <asm/mach-types.h>

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28#include <plat/clkdev_omap.h>
29
30#include "clock.h"
31#include "opp.h"
32
33__u32 arm_idlect1_mask;
34struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
35
37/*-------------------------------------------------------------------------
36/*
38 * Omap1 specific clock functions
37 * Omap1 specific clock functions
39 *-------------------------------------------------------------------------*/
38 */
40
41unsigned long omap1_uart_recalc(struct clk *clk)
42{
43 unsigned int val = __raw_readl(clk->enable_reg);
44 return val & clk->enable_bit ? 48000000 : 12000000;
45}
46
47unsigned long omap1_sossi_recalc(struct clk *clk)

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518 }
519}
520
521const struct clkops clkops_dspck = {
522 .enable = omap1_clk_enable_dsp_domain,
523 .disable = omap1_clk_disable_dsp_domain,
524};
525
39
40unsigned long omap1_uart_recalc(struct clk *clk)
41{
42 unsigned int val = __raw_readl(clk->enable_reg);
43 return val & clk->enable_bit ? 48000000 : 12000000;
44}
45
46unsigned long omap1_sossi_recalc(struct clk *clk)

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517 }
518}
519
520const struct clkops clkops_dspck = {
521 .enable = omap1_clk_enable_dsp_domain,
522 .disable = omap1_clk_disable_dsp_domain,
523};
524
526static int omap1_clk_enable_uart_functional(struct clk *clk)
525/* XXX SYSC register handling does not belong in the clock framework */
526static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
527{
528 int ret;
529 struct uart_clk *uclk;
530
531 ret = omap1_clk_enable_generic(clk);
532 if (ret == 0) {
533 /* Set smart idle acknowledgement mode */
534 uclk = (struct uart_clk *)clk;
535 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
536 uclk->sysc_addr);
537 }
538
539 return ret;
540}
541
527{
528 int ret;
529 struct uart_clk *uclk;
530
531 ret = omap1_clk_enable_generic(clk);
532 if (ret == 0) {
533 /* Set smart idle acknowledgement mode */
534 uclk = (struct uart_clk *)clk;
535 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
536 uclk->sysc_addr);
537 }
538
539 return ret;
540}
541
542static void omap1_clk_disable_uart_functional(struct clk *clk)
542/* XXX SYSC register handling does not belong in the clock framework */
543static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
543{
544 struct uart_clk *uclk;
545
546 /* Set force idle acknowledgement mode */
547 uclk = (struct uart_clk *)clk;
548 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
549
550 omap1_clk_disable_generic(clk);
551}
552
544{
545 struct uart_clk *uclk;
546
547 /* Set force idle acknowledgement mode */
548 uclk = (struct uart_clk *)clk;
549 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
550
551 omap1_clk_disable_generic(clk);
552}
553
553const struct clkops clkops_uart = {
554 .enable = omap1_clk_enable_uart_functional,
555 .disable = omap1_clk_disable_uart_functional,
554/* XXX SYSC register handling does not belong in the clock framework */
555const struct clkops clkops_uart_16xx = {
556 .enable = omap1_clk_enable_uart_functional_16xx,
557 .disable = omap1_clk_disable_uart_functional_16xx,
556};
557
558long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
559{
560 if (clk->round_rate != NULL)
561 return clk->round_rate(clk, rate);
562
563 return clk->rate;
564}
565
566int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
567{
568 int ret = -EINVAL;
569
570 if (clk->set_rate)
571 ret = clk->set_rate(clk, rate);
572 return ret;
573}
574
558};
559
560long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
561{
562 if (clk->round_rate != NULL)
563 return clk->round_rate(clk, rate);
564
565 return clk->rate;
566}
567
568int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
569{
570 int ret = -EINVAL;
571
572 if (clk->set_rate)
573 ret = clk->set_rate(clk, rate);
574 return ret;
575}
576
575/*-------------------------------------------------------------------------
577/*
576 * Omap1 clock reset and init functions
578 * Omap1 clock reset and init functions
577 *-------------------------------------------------------------------------*/
579 */
578
579#ifdef CONFIG_OMAP_RESET_CLOCKS
580
581void omap1_clk_disable_unused(struct clk *clk)
582{
583 __u32 regval32;
584
585 /* Clocks in the DSP domain need api_ck. Just assume bootloader

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581#ifdef CONFIG_OMAP_RESET_CLOCKS
582
583void omap1_clk_disable_unused(struct clk *clk)
584{
585 __u32 regval32;
586
587 /* Clocks in the DSP domain need api_ck. Just assume bootloader

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