time.c (eadb8a091b27a840de7450f84ecff5ef13476424) time.c (2f7e8faef5a50efaa1c173e99bdaa29e0129bb99)
1/*
2 * linux/arch/arm/mach-mmp/time.c
3 *
4 * Support for clocksource and clockevents
5 *
6 * Copyright (C) 2008 Marvell International Ltd.
7 * All rights reserved.
8 *

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25
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/cnt32_to_63.h>
30
31#include <mach/addr-map.h>
32#include <mach/regs-timers.h>
1/*
2 * linux/arch/arm/mach-mmp/time.c
3 *
4 * Support for clocksource and clockevents
5 *
6 * Copyright (C) 2008 Marvell International Ltd.
7 * All rights reserved.
8 *

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25
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/sched.h>
29#include <linux/cnt32_to_63.h>
30
31#include <mach/addr-map.h>
32#include <mach/regs-timers.h>
33#include <mach/regs-apbc.h>
33#include <mach/irqs.h>
34#include <mach/irqs.h>
35#include <mach/cputype.h>
36#include <asm/mach/time.h>
34
35#include "clock.h"
36
37#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
38
39#define MAX_DELTA (0xfffffffe)
40#define MIN_DELTA (16)
41

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153static void __init timer_config(void)
154{
155 uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
156 uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER);
157 uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR);
158
159 __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
160
37
38#include "clock.h"
39
40#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
41
42#define MAX_DELTA (0xfffffffe)
43#define MIN_DELTA (16)
44

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156static void __init timer_config(void)
157{
158 uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
159 uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER);
160 uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR);
161
162 __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
163
161 ccr &= TMR_CCR_CS_0(0x3);
164 ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3);
162 __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
163
164 /* free-running mode */
165 __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR);
166
167 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */
168 __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
169 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));

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192
193 cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
194
195 setup_irq(irq, &timer_irq);
196
197 clocksource_register(&cksrc);
198 clockevents_register_device(&ckevt);
199}
165 __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
166
167 /* free-running mode */
168 __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR);
169
170 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */
171 __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
172 __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));

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195
196 cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
197
198 setup_irq(irq, &timer_irq);
199
200 clocksource_register(&cksrc);
201 clockevents_register_device(&ckevt);
202}
203
204static void __init mmp2_timer_init(void)
205{
206 unsigned long clk_rst;
207
208 __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
209
210 /*
211 * enable bus/functional clock, enable 6.5MHz (divider 4),
212 * release reset
213 */
214 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
215 __raw_writel(clk_rst, APBC_MMP2_TIMERS);
216
217 timer_init(IRQ_MMP2_TIMER1);
218}
219
220struct sys_timer mmp2_timer = {
221 .init = mmp2_timer_init,
222};
223