time.c (407da561244b9d51e6a794d6305ba38ec2c9d907) time.c (77acc85ce797a4a19a46c9677dec5a9910c6e4e7)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-mmp/time.c
4 *
5 * Support for clocksource and clockevents
6 *
7 * Copyright (C) 2008 Marvell International Ltd.
8 * All rights reserved.

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24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/sched_clock.h>
30#include <asm/mach/time.h>
31
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-mmp/time.c
4 *
5 * Support for clocksource and clockevents
6 *
7 * Copyright (C) 2008 Marvell International Ltd.
8 * All rights reserved.

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24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/sched_clock.h>
30#include <asm/mach/time.h>
31
32#include "addr-map.h"
33#include "regs-timers.h"
32#include "regs-timers.h"
34#include "regs-apbc.h"
35#include "irqs.h"
36#include <linux/soc/mmp/cputype.h>
37
33#include <linux/soc/mmp/cputype.h>
34
38#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
39
40#define MAX_DELTA (0xfffffffe)
41#define MIN_DELTA (16)
42
35#define MAX_DELTA (0xfffffffe)
36#define MIN_DELTA (16)
37
43static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
38static void __iomem *mmp_timer_base;
44
45/*
46 * Read the timer through the CVWR register. Delay is required after requesting
47 * a read. The CR register cannot be directly read due to metastability issues
48 * documented in the PXA168 software manual.
49 */
50static inline uint32_t timer_read(void)
51{

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172 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
173 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
174 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
175
176 /* enable timer 1 counter */
177 __raw_writel(0x2, mmp_timer_base + TMR_CER);
178}
179
39
40/*
41 * Read the timer through the CVWR register. Delay is required after requesting
42 * a read. The CR register cannot be directly read due to metastability issues
43 * documented in the PXA168 software manual.
44 */
45static inline uint32_t timer_read(void)
46{

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167 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
168 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
169 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
170
171 /* enable timer 1 counter */
172 __raw_writel(0x2, mmp_timer_base + TMR_CER);
173}
174
180void __init mmp_timer_init(int irq, unsigned long rate)
175static void __init mmp_timer_init(int irq, unsigned long rate)
181{
182 timer_config();
183
184 sched_clock_register(mmp_read_sched_clock, 32, rate);
185
186 ckevt.cpumask = cpumask_of(0);
187
188 if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,

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177 timer_config();
178
179 sched_clock_register(mmp_read_sched_clock, 32, rate);
180
181 ckevt.cpumask = cpumask_of(0);
182
183 if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,

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