tzic.c (4ba24fef3eb3b142197135223b90ced2f319cd53) tzic.c (c553138fbd1ee193a19101a36fb0814607ab4e7b)
1/*
2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html

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60{
61 unsigned int index, mask, value;
62
63 index = irq >> 5;
64 if (unlikely(index >= 4))
65 return -EINVAL;
66 mask = 1U << (irq & 0x1F);
67
1/*
2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html

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60{
61 unsigned int index, mask, value;
62
63 index = irq >> 5;
64 if (unlikely(index >= 4))
65 return -EINVAL;
66 mask = 1U << (irq & 0x1F);
67
68 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
68 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
69 if (type)
70 value &= ~mask;
69 if (type)
70 value &= ~mask;
71 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
71 imx_writel(value, tzic_base + TZIC_INTSEC0(index));
72
73 return 0;
74}
75#else
76#define tzic_set_irq_fiq NULL
77#endif
78
79#ifdef CONFIG_PM
80static void tzic_irq_suspend(struct irq_data *d)
81{
82 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
83 int idx = d->hwirq >> 5;
84
72
73 return 0;
74}
75#else
76#define tzic_set_irq_fiq NULL
77#endif
78
79#ifdef CONFIG_PM
80static void tzic_irq_suspend(struct irq_data *d)
81{
82 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
83 int idx = d->hwirq >> 5;
84
85 __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
85 imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
86}
87
88static void tzic_irq_resume(struct irq_data *d)
89{
90 int idx = d->hwirq >> 5;
91
86}
87
88static void tzic_irq_resume(struct irq_data *d)
89{
90 int idx = d->hwirq >> 5;
91
92 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
93 tzic_base + TZIC_WAKEUP0(idx));
92 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)),
93 tzic_base + TZIC_WAKEUP0(idx));
94}
95
96#else
97#define tzic_irq_suspend NULL
98#define tzic_irq_resume NULL
99#endif
100
101static struct mxc_extra_irq tzic_extra_irq = {

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130{
131 u32 stat;
132 int i, irqofs, handled;
133
134 do {
135 handled = 0;
136
137 for (i = 0; i < 4; i++) {
94}
95
96#else
97#define tzic_irq_suspend NULL
98#define tzic_irq_resume NULL
99#endif
100
101static struct mxc_extra_irq tzic_extra_irq = {

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130{
131 u32 stat;
132 int i, irqofs, handled;
133
134 do {
135 handled = 0;
136
137 for (i = 0; i < 4; i++) {
138 stat = __raw_readl(tzic_base + TZIC_HIPND(i)) &
139 __raw_readl(tzic_base + TZIC_INTSEC0(i));
138 stat = imx_readl(tzic_base + TZIC_HIPND(i)) &
139 imx_readl(tzic_base + TZIC_INTSEC0(i));
140
141 while (stat) {
142 handled = 1;
143 irqofs = fls(stat) - 1;
144 handle_domain_irq(domain, irqofs + i * 32, regs);
145 stat &= ~(1 << irqofs);
146 }
147 }

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161
162 np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
163 tzic_base = of_iomap(np, 0);
164 WARN_ON(!tzic_base);
165
166 /* put the TZIC into the reset value with
167 * all interrupts disabled
168 */
140
141 while (stat) {
142 handled = 1;
143 irqofs = fls(stat) - 1;
144 handle_domain_irq(domain, irqofs + i * 32, regs);
145 stat &= ~(1 << irqofs);
146 }
147 }

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161
162 np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
163 tzic_base = of_iomap(np, 0);
164 WARN_ON(!tzic_base);
165
166 /* put the TZIC into the reset value with
167 * all interrupts disabled
168 */
169 i = __raw_readl(tzic_base + TZIC_INTCNTL);
169 i = imx_readl(tzic_base + TZIC_INTCNTL);
170
170
171 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
172 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
173 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
171 imx_writel(0x80010001, tzic_base + TZIC_INTCNTL);
172 imx_writel(0x1f, tzic_base + TZIC_PRIOMASK);
173 imx_writel(0x02, tzic_base + TZIC_SYNCCTRL);
174
175 for (i = 0; i < 4; i++)
174
175 for (i = 0; i < 4; i++)
176 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
176 imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
177
178 /* disable all interrupts */
179 for (i = 0; i < 4; i++)
177
178 /* disable all interrupts */
179 for (i = 0; i < 4; i++)
180 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
180 imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
181
182 /* all IRQ no FIQ Warning :: No selection */
183
184 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
185 WARN_ON(irq_base < 0);
186
187 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
188 &irq_domain_simple_ops, NULL);

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209 * This function provides an interrupt synchronization point that is required
210 * by tzic enabled platforms before entering imx specific low power modes (ie,
211 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
212 */
213int tzic_enable_wake(void)
214{
215 unsigned int i;
216
181
182 /* all IRQ no FIQ Warning :: No selection */
183
184 irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
185 WARN_ON(irq_base < 0);
186
187 domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
188 &irq_domain_simple_ops, NULL);

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209 * This function provides an interrupt synchronization point that is required
210 * by tzic enabled platforms before entering imx specific low power modes (ie,
211 * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
212 */
213int tzic_enable_wake(void)
214{
215 unsigned int i;
216
217 __raw_writel(1, tzic_base + TZIC_DSMINT);
218 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
217 imx_writel(1, tzic_base + TZIC_DSMINT);
218 if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0))
219 return -EAGAIN;
220
221 for (i = 0; i < 4; i++)
219 return -EAGAIN;
220
221 for (i = 0; i < 4; i++)
222 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
223 tzic_base + TZIC_WAKEUP0(i));
222 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)),
223 tzic_base + TZIC_WAKEUP0(i));
224
225 return 0;
226}
224
225 return 0;
226}