mxc.h (db985cbd67c45f875ef43cb5febfaa8cbd203c27) mxc.h (c896e938505714d4346388ddc8a82fb190f235aa)
1/*
2 * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.

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38#define MXC_CPU_IMX6DL 0x61
39#define MXC_CPU_IMX6SX 0x62
40#define MXC_CPU_IMX6Q 0x63
41
42#define IMX_CHIP_REVISION_1_0 0x10
43#define IMX_CHIP_REVISION_1_1 0x11
44#define IMX_CHIP_REVISION_1_2 0x12
45#define IMX_CHIP_REVISION_1_3 0x13
1/*
2 * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.

--- 29 unchanged lines hidden (view full) ---

38#define MXC_CPU_IMX6DL 0x61
39#define MXC_CPU_IMX6SX 0x62
40#define MXC_CPU_IMX6Q 0x63
41
42#define IMX_CHIP_REVISION_1_0 0x10
43#define IMX_CHIP_REVISION_1_1 0x11
44#define IMX_CHIP_REVISION_1_2 0x12
45#define IMX_CHIP_REVISION_1_3 0x13
46#define IMX_CHIP_REVISION_1_4 0x14
47#define IMX_CHIP_REVISION_1_5 0x15
46#define IMX_CHIP_REVISION_2_0 0x20
47#define IMX_CHIP_REVISION_2_1 0x21
48#define IMX_CHIP_REVISION_2_2 0x22
49#define IMX_CHIP_REVISION_2_3 0x23
50#define IMX_CHIP_REVISION_3_0 0x30
51#define IMX_CHIP_REVISION_3_1 0x31
52#define IMX_CHIP_REVISION_3_2 0x32
53#define IMX_CHIP_REVISION_3_3 0x33

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48#define IMX_CHIP_REVISION_2_0 0x20
49#define IMX_CHIP_REVISION_2_1 0x21
50#define IMX_CHIP_REVISION_2_2 0x22
51#define IMX_CHIP_REVISION_2_3 0x23
52#define IMX_CHIP_REVISION_3_0 0x30
53#define IMX_CHIP_REVISION_3_1 0x31
54#define IMX_CHIP_REVISION_3_2 0x32
55#define IMX_CHIP_REVISION_3_3 0x33

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