| common.h (08ae9646468c636098f689a72194778b15c9d94a) | common.h (ec336b284136610a43c9daac56d66b20d43ddf7b) |
|---|---|
| 1/* 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. 3 */ 4 5/* 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 47 unchanged lines hidden (view full) --- 56int mx31_clocks_init(unsigned long fref); 57int mx35_clocks_init(void); 58int mx31_clocks_init_dt(void); 59struct platform_device *mxc_register_gpio(char *name, int id, 60 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); 61void mxc_set_cpu_type(unsigned int type); 62void mxc_restart(enum reboot_mode, const char *); 63void mxc_arch_reset_init(void __iomem *); | 1/* 2 * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. 3 */ 4 5/* 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 47 unchanged lines hidden (view full) --- 56int mx31_clocks_init(unsigned long fref); 57int mx35_clocks_init(void); 58int mx31_clocks_init_dt(void); 59struct platform_device *mxc_register_gpio(char *name, int id, 60 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); 61void mxc_set_cpu_type(unsigned int type); 62void mxc_restart(enum reboot_mode, const char *); 63void mxc_arch_reset_init(void __iomem *); |
| 64void mxc_arch_reset_init_dt(void); |
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| 64int mx51_revision(void); 65int mx53_revision(void); 66void imx_set_aips(void __iomem *); 67void imx_aips_allow_unprivileged_access(const char *compat); 68int mxc_device_init(void); 69void imx_set_soc_revision(unsigned int rev); 70unsigned int imx_get_soc_revision(void); 71void imx_init_revision_from_anatop(void); --- 38 unchanged lines hidden (view full) --- 110void imx_gpc_irq_mask(struct irq_data *d); 111void imx_gpc_irq_unmask(struct irq_data *d); 112void imx_anatop_init(void); 113void imx_anatop_pre_suspend(void); 114void imx_anatop_post_resume(void); 115int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 116void imx6q_set_int_mem_clk_lpm(bool enable); 117void imx6sl_set_wait_clk(bool enter); | 65int mx51_revision(void); 66int mx53_revision(void); 67void imx_set_aips(void __iomem *); 68void imx_aips_allow_unprivileged_access(const char *compat); 69int mxc_device_init(void); 70void imx_set_soc_revision(unsigned int rev); 71unsigned int imx_get_soc_revision(void); 72void imx_init_revision_from_anatop(void); --- 38 unchanged lines hidden (view full) --- 111void imx_gpc_irq_mask(struct irq_data *d); 112void imx_gpc_irq_unmask(struct irq_data *d); 113void imx_anatop_init(void); 114void imx_anatop_pre_suspend(void); 115void imx_anatop_post_resume(void); 116int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 117void imx6q_set_int_mem_clk_lpm(bool enable); 118void imx6sl_set_wait_clk(bool enter); |
| 119int imx_mmdc_get_ddr_type(void); |
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| 118 119void imx_cpu_die(unsigned int cpu); 120int imx_cpu_kill(unsigned int cpu); 121 122#ifdef CONFIG_SUSPEND 123void v7_cpu_resume(void); 124void imx6_suspend(void __iomem *ocram_vbase); 125#else --- 35 unchanged lines hidden --- | 120 121void imx_cpu_die(unsigned int cpu); 122int imx_cpu_kill(unsigned int cpu); 123 124#ifdef CONFIG_SUSPEND 125void v7_cpu_resume(void); 126void imx6_suspend(void __iomem *ocram_vbase); 127#else --- 35 unchanged lines hidden --- |