avic.c (4ba24fef3eb3b142197135223b90ced2f319cd53) avic.c (c553138fbd1ee193a19101a36fb0814607ab4e7b)
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.

--- 52 unchanged lines hidden (view full) ---

61 unsigned int irqt;
62
63 irq = d->hwirq;
64
65 if (irq >= AVIC_NUM_IRQS)
66 return -EINVAL;
67
68 if (irq < AVIC_NUM_IRQS / 2) {
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.

--- 52 unchanged lines hidden (view full) ---

61 unsigned int irqt;
62
63 irq = d->hwirq;
64
65 if (irq >= AVIC_NUM_IRQS)
66 return -EINVAL;
67
68 if (irq < AVIC_NUM_IRQS / 2) {
69 irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
70 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
69 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
70 imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
71 } else {
72 irq -= AVIC_NUM_IRQS / 2;
71 } else {
72 irq -= AVIC_NUM_IRQS / 2;
73 irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
74 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
73 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
74 imx_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
75 }
76
77 return 0;
78}
79#endif /* CONFIG_FIQ */
80
81
82static struct mxc_extra_irq avic_extra_irq = {

--- 6 unchanged lines hidden (view full) ---

89static u32 avic_saved_mask_reg[2];
90
91static void avic_irq_suspend(struct irq_data *d)
92{
93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
94 struct irq_chip_type *ct = gc->chip_types;
95 int idx = d->hwirq >> 5;
96
75 }
76
77 return 0;
78}
79#endif /* CONFIG_FIQ */
80
81
82static struct mxc_extra_irq avic_extra_irq = {

--- 6 unchanged lines hidden (view full) ---

89static u32 avic_saved_mask_reg[2];
90
91static void avic_irq_suspend(struct irq_data *d)
92{
93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
94 struct irq_chip_type *ct = gc->chip_types;
95 int idx = d->hwirq >> 5;
96
97 avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
98 __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
97 avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
98 imx_writel(gc->wake_active, avic_base + ct->regs.mask);
99}
100
101static void avic_irq_resume(struct irq_data *d)
102{
103 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
104 struct irq_chip_type *ct = gc->chip_types;
105 int idx = d->hwirq >> 5;
106
99}
100
101static void avic_irq_resume(struct irq_data *d)
102{
103 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
104 struct irq_chip_type *ct = gc->chip_types;
105 int idx = d->hwirq >> 5;
106
107 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
107 imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
108}
109
110#else
111#define avic_irq_suspend NULL
112#define avic_irq_resume NULL
113#endif
114
115static __init void avic_init_gc(int idx, unsigned int irq_start)

--- 19 unchanged lines hidden (view full) ---

135 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
136}
137
138static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
139{
140 u32 nivector;
141
142 do {
108}
109
110#else
111#define avic_irq_suspend NULL
112#define avic_irq_resume NULL
113#endif
114
115static __init void avic_init_gc(int idx, unsigned int irq_start)

--- 19 unchanged lines hidden (view full) ---

135 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
136}
137
138static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
139{
140 u32 nivector;
141
142 do {
143 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
143 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
144 if (nivector == 0xffff)
145 break;
146
147 handle_domain_irq(domain, nivector, regs);
148 } while (1);
149}
150
151/*

--- 7 unchanged lines hidden (view full) ---

159 int irq_base;
160 int i;
161
162 avic_base = irqbase;
163
164 /* put the AVIC into the reset value with
165 * all interrupts disabled
166 */
144 if (nivector == 0xffff)
145 break;
146
147 handle_domain_irq(domain, nivector, regs);
148 } while (1);
149}
150
151/*

--- 7 unchanged lines hidden (view full) ---

159 int irq_base;
160 int i;
161
162 avic_base = irqbase;
163
164 /* put the AVIC into the reset value with
165 * all interrupts disabled
166 */
167 __raw_writel(0, avic_base + AVIC_INTCNTL);
168 __raw_writel(0x1f, avic_base + AVIC_NIMASK);
167 imx_writel(0, avic_base + AVIC_INTCNTL);
168 imx_writel(0x1f, avic_base + AVIC_NIMASK);
169
170 /* disable all interrupts */
169
170 /* disable all interrupts */
171 __raw_writel(0, avic_base + AVIC_INTENABLEH);
172 __raw_writel(0, avic_base + AVIC_INTENABLEL);
171 imx_writel(0, avic_base + AVIC_INTENABLEH);
172 imx_writel(0, avic_base + AVIC_INTENABLEL);
173
174 /* all IRQ no FIQ */
173
174 /* all IRQ no FIQ */
175 __raw_writel(0, avic_base + AVIC_INTTYPEH);
176 __raw_writel(0, avic_base + AVIC_INTTYPEL);
175 imx_writel(0, avic_base + AVIC_INTTYPEH);
176 imx_writel(0, avic_base + AVIC_INTTYPEL);
177
178 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
179 WARN_ON(irq_base < 0);
180
181 np = of_find_compatible_node(NULL, NULL, "fsl,avic");
182 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
183 &irq_domain_simple_ops, NULL);
184 WARN_ON(!domain);
185
186 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
187 avic_init_gc(i, irq_base);
188
189 /* Set default priority value (0) for all IRQ's */
190 for (i = 0; i < 8; i++)
177
178 irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
179 WARN_ON(irq_base < 0);
180
181 np = of_find_compatible_node(NULL, NULL, "fsl,avic");
182 domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
183 &irq_domain_simple_ops, NULL);
184 WARN_ON(!domain);
185
186 for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
187 avic_init_gc(i, irq_base);
188
189 /* Set default priority value (0) for all IRQ's */
190 for (i = 0; i < 8; i++)
191 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
191 imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
192
193 set_handle_irq(avic_handle_irq);
194
195#ifdef CONFIG_FIQ
196 /* Initialize FIQ */
197 init_FIQ(FIQ_START);
198#endif
199
200 printk(KERN_INFO "MXC IRQ initialized\n");
201}
192
193 set_handle_irq(avic_handle_irq);
194
195#ifdef CONFIG_FIQ
196 /* Initialize FIQ */
197 init_FIQ(FIQ_START);
198#endif
199
200 printk(KERN_INFO "MXC IRQ initialized\n");
201}