hotplug.c (f01387d2693813eb5271a3448e6a082322c7d75d) hotplug.c (06cc5c1d4d7313bc864e9aac1d1cbd63d8b9ca4c)
1/*
2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */

--- 43 unchanged lines hidden (view full) ---

52 * CPU1_SRST_REQ_EN (1 << 1)
53 * ...
54 */
55#define CPU0_HPM_SRST_REQ_EN (1 << 22)
56#define CPU0_DBG_SRST_REQ_EN (1 << 12)
57#define CPU0_NEON_SRST_REQ_EN (1 << 4)
58#define CPU0_SRST_REQ_EN (1 << 0)
59
1/*
2 * Copyright (c) 2013 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */

--- 43 unchanged lines hidden (view full) ---

52 * CPU1_SRST_REQ_EN (1 << 1)
53 * ...
54 */
55#define CPU0_HPM_SRST_REQ_EN (1 << 22)
56#define CPU0_DBG_SRST_REQ_EN (1 << 12)
57#define CPU0_NEON_SRST_REQ_EN (1 << 4)
58#define CPU0_SRST_REQ_EN (1 << 0)
59
60#define HIX5HD2_PERI_CRG20 0x50
61#define CRG20_CPU1_RESET (1 << 17)
62
63#define HIX5HD2_PERI_PMC0 0x1000
64#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
65#define PMC0_CPU1_PMC_ENABLE (1 << 7)
66#define PMC0_CPU1_POWERDOWN (1 << 3)
67
60enum {
61 HI3620_CTRL,
62 ERROR_CTRL,
63};
64
65static void __iomem *ctrl_base;
66static int id;
67

--- 84 unchanged lines hidden (view full) ---

152 if (hi3xxx_hotplug_init() < 0)
153 return;
154 }
155
156 if (id == HI3620_CTRL)
157 set_cpu_hi3620(cpu, enable);
158}
159
68enum {
69 HI3620_CTRL,
70 ERROR_CTRL,
71};
72
73static void __iomem *ctrl_base;
74static int id;
75

--- 84 unchanged lines hidden (view full) ---

160 if (hi3xxx_hotplug_init() < 0)
161 return;
162 }
163
164 if (id == HI3620_CTRL)
165 set_cpu_hi3620(cpu, enable);
166}
167
168static bool hix5hd2_hotplug_init(void)
169{
170 struct device_node *np;
171
172 np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
173 if (np) {
174 ctrl_base = of_iomap(np, 0);
175 return true;
176 }
177 return false;
178}
179
180void hix5hd2_set_cpu(int cpu, bool enable)
181{
182 u32 val = 0;
183
184 if (!ctrl_base)
185 if (!hix5hd2_hotplug_init())
186 BUG();
187
188 if (enable) {
189 /* power on cpu1 */
190 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
191 val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
192 val |= PMC0_CPU1_PMC_ENABLE;
193 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
194 /* unreset */
195 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
196 val &= ~CRG20_CPU1_RESET;
197 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
198 } else {
199 /* power down cpu1 */
200 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
201 val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
202 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
203 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
204
205 /* reset */
206 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
207 val |= CRG20_CPU1_RESET;
208 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
209 }
210}
211
160static inline void cpu_enter_lowpower(void)
161{
162 unsigned int v;
163
164 flush_cache_all();
165
166 /*
167 * Turn off coherency and L1 D-cache

--- 26 unchanged lines hidden (view full) ---

194 unsigned long timeout = jiffies + msecs_to_jiffies(50);
195
196 while (hi3xxx_get_cpu_jump(cpu))
197 if (time_after(jiffies, timeout))
198 return 0;
199 hi3xxx_set_cpu(cpu, false);
200 return 1;
201}
212static inline void cpu_enter_lowpower(void)
213{
214 unsigned int v;
215
216 flush_cache_all();
217
218 /*
219 * Turn off coherency and L1 D-cache

--- 26 unchanged lines hidden (view full) ---

246 unsigned long timeout = jiffies + msecs_to_jiffies(50);
247
248 while (hi3xxx_get_cpu_jump(cpu))
249 if (time_after(jiffies, timeout))
250 return 0;
251 hi3xxx_set_cpu(cpu, false);
252 return 1;
253}
254
255void hix5hd2_cpu_die(unsigned int cpu)
256{
257 flush_cache_all();
258 hix5hd2_set_cpu(cpu, false);
259}
202#endif
260#endif