sysregs.h (da733563be5a9da26fe81d9f007262d00b846e22) sysregs.h (7a2848d369b2b9281400e6c9f08e21ec71cd1dcb)
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef _MACH_HIGHBANK__SYSREGS_H_
17#define _MACH_HIGHBANK__SYSREGS_H_
18
19#include <linux/io.h>
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef _MACH_HIGHBANK__SYSREGS_H_
17#define _MACH_HIGHBANK__SYSREGS_H_
18
19#include <linux/io.h>
20#include <linux/smp.h>
21#include <asm/smp_plat.h>
22#include <asm/smp_scu.h>
23#include "core.h"
20
21extern void __iomem *sregs_base;
22
23#define HB_SREG_A9_PWR_REQ 0xf00
24#define HB_SREG_A9_BOOT_STAT 0xf04
25#define HB_SREG_A9_BOOT_DATA 0xf08
26
27#define HB_PWR_SUSPEND 0
28#define HB_PWR_SOFT_RESET 1
29#define HB_PWR_HARD_RESET 2
30#define HB_PWR_SHUTDOWN 3
31
24
25extern void __iomem *sregs_base;
26
27#define HB_SREG_A9_PWR_REQ 0xf00
28#define HB_SREG_A9_BOOT_STAT 0xf04
29#define HB_SREG_A9_BOOT_DATA 0xf08
30
31#define HB_PWR_SUSPEND 0
32#define HB_PWR_SOFT_RESET 1
33#define HB_PWR_HARD_RESET 2
34#define HB_PWR_SHUTDOWN 3
35
36#define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
37
38static inline void highbank_set_core_pwr(void)
39{
40 int cpu = cpu_logical_map(smp_processor_id());
41 if (scu_base_addr)
42 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
43 else
44 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
45}
46
32static inline void hignbank_set_pwr_suspend(void)
33{
34 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
47static inline void hignbank_set_pwr_suspend(void)
48{
49 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
50 highbank_set_core_pwr();
35}
36
37static inline void hignbank_set_pwr_shutdown(void)
38{
39 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
51}
52
53static inline void hignbank_set_pwr_shutdown(void)
54{
55 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
56 highbank_set_core_pwr();
40}
41
42static inline void hignbank_set_pwr_soft_reset(void)
43{
44 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
57}
58
59static inline void hignbank_set_pwr_soft_reset(void)
60{
61 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
62 highbank_set_core_pwr();
45}
46
47static inline void hignbank_set_pwr_hard_reset(void)
48{
49 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
63}
64
65static inline void hignbank_set_pwr_hard_reset(void)
66{
67 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
68 highbank_set_core_pwr();
50}
51
52#endif
69}
70
71#endif