sysregs.h (c05ee88f6f20746aff938a85ef49e777ef4c6513) sysregs.h (9852910a0b0aa5548f990b51ad335921e0a710bf)
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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39{
40 int cpu = cpu_logical_map(smp_processor_id());
41 if (scu_base_addr)
42 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
43 else
44 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
45}
46
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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39{
40 int cpu = cpu_logical_map(smp_processor_id());
41 if (scu_base_addr)
42 scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
43 else
44 writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
45}
46
47static inline void highbank_clear_core_pwr(void)
48{
49 int cpu = cpu_logical_map(smp_processor_id());
50 if (scu_base_addr)
51 scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
52 else
53 writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
54}
55
47static inline void highbank_set_pwr_suspend(void)
48{
49 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
50 highbank_set_core_pwr();
51}
52
53static inline void highbank_set_pwr_shutdown(void)
54{

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63}
64
65static inline void highbank_set_pwr_hard_reset(void)
66{
67 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
68 highbank_set_core_pwr();
69}
70
56static inline void highbank_set_pwr_suspend(void)
57{
58 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
59 highbank_set_core_pwr();
60}
61
62static inline void highbank_set_pwr_shutdown(void)
63{

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72}
73
74static inline void highbank_set_pwr_hard_reset(void)
75{
76 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
77 highbank_set_core_pwr();
78}
79
80static inline void highbank_clear_pwr_request(void)
81{
82 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
83 highbank_clear_core_pwr();
84}
85
71#endif
86#endif