common.c (7266d48fca8ee2a15d15222c41f887e10db54c5a) common.c (48be9ac930086f7605fb4959936f568e865b2cff)
1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

--- 346 unchanged lines hidden (view full) ---

355 /*
356 * Assert soft reset.
357 */
358 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
359
360 while (1)
361 ;
362}
1/*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

--- 346 unchanged lines hidden (view full) ---

355 /*
356 * Assert soft reset.
357 */
358 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
359
360 while (1)
361 ;
362}
363
364#if defined(CONFIG_MACH_DOVE_DT)
365/*
366 * There are still devices that doesn't even know about DT,
367 * get clock gates here and add a clock lookup.
368 */
369static void __init dove_legacy_clk_init(void)
370{
371 struct device_node *np = of_find_compatible_node(NULL, NULL,
372 "marvell,dove-gating-clock");
373 struct of_phandle_args clkspec;
374
375 clkspec.np = np;
376 clkspec.args_count = 1;
377
378 clkspec.args[0] = CLOCK_GATING_BIT_USB0;
379 orion_clkdev_add(NULL, "orion-ehci.0",
380 of_clk_get_from_provider(&clkspec));
381
382 clkspec.args[0] = CLOCK_GATING_BIT_USB1;
383 orion_clkdev_add(NULL, "orion-ehci.1",
384 of_clk_get_from_provider(&clkspec));
385
386 clkspec.args[0] = CLOCK_GATING_BIT_GBE;
387 orion_clkdev_add(NULL, "mv643xx_eth_port.0",
388 of_clk_get_from_provider(&clkspec));
389
390 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
391 orion_clkdev_add("0", "pcie",
392 of_clk_get_from_provider(&clkspec));
393
394 clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
395 orion_clkdev_add("1", "pcie",
396 of_clk_get_from_provider(&clkspec));
397}
398
399static void __init dove_of_clk_init(void)
400{
401 mvebu_clocks_init();
402 dove_legacy_clk_init();
403}
404
405static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
406 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
407};
408
409static void __init dove_dt_init(void)
410{
411 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
412 (dove_tclk + 499999) / 1000000);
413
414#ifdef CONFIG_CACHE_TAUROS2
415 tauros2_init(0);
416#endif
417 dove_setup_cpu_mbus();
418
419 /* Setup root of clk tree */
420 dove_of_clk_init();
421
422 /* Internal devices not ported to DT yet */
423 dove_rtc_init();
424
425 dove_ge00_init(&dove_dt_ge00_data);
426 dove_ehci0_init();
427 dove_ehci1_init();
428 dove_pcie_init(1, 1);
429
430 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
431}
432
433static const char * const dove_dt_board_compat[] = {
434 "marvell,dove",
435 NULL
436};
437
438DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
439 .map_io = dove_map_io,
440 .init_early = dove_init_early,
441 .init_irq = orion_dt_init_irq,
442 .init_time = dove_timer_init,
443 .init_machine = dove_dt_init,
444 .restart = dove_restart,
445 .dt_compat = dove_dt_board_compat,
446MACHINE_END
447#endif